The conventional (plug-less) and tungsten (W) plug contact interconnect techndogies were studied for the fabrication of 0.85 pm CMOS EPROM integrated Circuit devices. 4 Mbit EPROM devices and appropriate test structures were fabricated using these two interconnect architectures and were evaluated for process simplicity, associated problemdsolutions, contact electrical characteristics, and circuit yield and speed. A TiN/Ti bi-layer film was used as a diffusion barrier (conventional process) and glue layer (W plug process). A strong adhesion bond between the TiN/Ti and the underlying BPTEOS films was required for the I.V plug process in order to withstand the tensile stress of the I.V film (3-439 dydcm'). In the absence of a strong adhesion bond, the T i " film would separate (peel off) from the oxide film during, or after deposition of the CV film. In order to eliminate peeling, the wafers with TiNPTi were subjected to a multi-step rapid thermal heat treatment process (RTHT) prior to W deposition. This process resulted in the formulation of a TiSi, compound, and consequently, a strong bond between the TiNfl3 and the B€"I'EOS films. The most important process issue for the conventional contact technology was the overlay accuracy of the stepper used for printing the eootacts. It was found that a misalignment of < 0.3pm was essential if contacts were to be refbwed after the contact etch process in a way that: a) did not violate the geometrical design rules, and b) did not result in bulging of the contacts, or an increase in the contact profile angle which would degrade metal step coverage.Electrical characteristics of the contacts were studied through contact resistance, specific contact resistivity, contact failure rate, and junction leakage measurements for both contact interconnect architectures. The data presented indicated that both processes produced contacts with similar characteristics.Finally, the results of this work indicated that the conventional contact interconnect technology could be reliably used for fabrication of 0.85 pm CMOS EPROM devices. This process was simpler, less expensive, and as structurally reliable as the I.F contact plug technology.