Advanced digital receiver principles and technologies for PCS

Integrated solutions for GSM terminals

“…A 'multiframe' (or cycle) allows for 26 successive bursts on a call (24 with traffic information-nomaally speech--and 2 for special purpose and control); it therefore lasts 26 • 4.615 ms = 120 ms. In this period eight users have each sent 24 packets of modulated data; in essence this multiframe is treated as a unit by the base station 9 The strange time periods arise from a desire for compatibility with ISDN (GSM was described as "mobile ISDN"), where it is important to have a synchronization which is some multiple of 20 ms; hence the 120 ms for a cycle (i.e., 0.577 ms is derived from 6 • 20 ms = 120 ms shared by 26 frames each with eight slots; i.e., 120/(26 x 8) = 0.577 ms). In fact, there are other types of multiframe (e.g., a 51 multiframe), and these are cascaded to form superframes and hyperframes.…”

High speed switched-capacitor analog correlator with balanced charge pump circuit for wired CDMA bus interface

“…At such a high bandwidth, reducing the signal voltage swing with the aim of reducing power consumption of the bus becomes more difficult because voltage swing is reduced at the cost of the noise margin [1][2][3]. Therefore, conventional Sonic (TDMA) style buses using tristate drivers are no longer adequate [4][5][6]. Aiming at solving the above issues, a new architecture using Code Division Multiple Access (CDMA) technique had been proposed [7].…”

A programmable power-efficient decimation filter for software radios

“…The lowpower techniques considered include operation minimization, datapath width optimization, multiplier elimination, and block deactivation. Figure 1 shows a typical receiver where the digitization is done after the first IF (Intermediate Frequency) stage [4]. The bottle neck of this architecture is the A/D (analog-todigital) converter.…”