Advanced fault isolation techniques for 3D packaging

Chen, Y.; Lai, Ping; Shi, Qiyun

doi:10.1109/ipfa.2016.7564284

“…3D packaging can be found in many forms, such as package-on-package (PoP), wafer level packaging (WLP), system-in-package (SiP), stacked-die packaging with wirebonds, through silicon vias (TSVs), interposers, etc. As a result, various non-destructive and destructive failure analysis techniques to access failures in 3D packaging has become increasingly challenging [1][2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Sample Preparation for Deprocessing of 3D Multi-Die Stacked Package

Kör

¹

,

Liu

²

,

Gan

³

2020

2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

0

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3D packaging consists of a variety of architectures and types. Fault isolation and physical failure analysis (PFA) can involve non-destructive and destructive techniques. Previously, decapsulation techniques to gain access to individual dice in a 3D multi-die stacked package with very thin dice (100 µm) had been investigated. This paper introduces the sample preparation techniques required for the deprocessing of a thin die within the 3D multi-die stacked package.

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2D/2.5D/3D Heterogeneous Integration

Endrinal,

Huat

2023

Electronic Device Failure Analysis Technology Roadmap

0

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Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

show abstract

2D/2.5D/3D Heterogeneous Integration

Endrinal,

Huat

2023

Electronic Device Failure Analysis Technology Roadmap

0

View full text Add to dashboard Cite

Recent trends in electronic packaging, including the growing use of 3D designs and heterogeneous integration, are greatly adding to the complexity of isolating faults in semiconductor products. This chapter reviews the latest IC packaging and integration solutions and assesses the readiness level of fault isolation tools and techniques. It examines the capabilities, limitations, and optimization potential of x-ray tomography and magnetic field imaging, describes various approaches for optical fault isolation, and compares and contrasts pre-OFI sample preparation methods. The chapter also explains how time-domain and electro-optical terahertz pulse reflectometry are used to find shorts and opens in ICs and how challenges related to heterogenous integration may be met through design for testability (DFT) and built-in self-test (BIST) accommodations and the use of passive interposers.

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Advanced fault isolation techniques for 3D packaging

Cited by 3 publications

References 12 publications

Sample Preparation for Deprocessing of 3D Multi-Die Stacked Package

Sample Preparation for Deprocessing of 3D Multi-Die Stacked Package

2D/2.5D/3D Heterogeneous Integration

2D/2.5D/3D Heterogeneous Integration

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