Advanced features in IBM POWER8 systems

Abstract

The IBM POWER8i processor includes many innovative features that enable efficient and flexible computing, along with enhancements in virtualization, security, and serviceability. These features benefit application performance, and big data and analytics computing, as well as the cloud environment. Notable features include the capabilities to dynamically and efficiently change the number of threads active on a processor, enhancing application performance via integer vector operations, encryption accelerations, and reference history arrays. Also notable is improved virtual machine density (supporting multiple simultaneous partitions per core and providing fine-grain power management), allowing continuous monitoring of system performance as well as significantly enhanced system RAS (reliability, availability, and serviceability) and security. Each of these features is technologically complex and advanced. This paper provides an in-depth description of some of these features and their exploitation through systems software and middleware. These features will continue to bring value to the system-of-record workloads in the enterprise. They also make POWER8 systems well-suited for serving the needs of newer workloads such as big data and analytics, while efficiently supporting deployment in cloud environments.

Security-first architecture: deploying physically isolated active security processors for safeguarding the future of computing

“…Leveraging the contention in memory resources including caches and TLBs etc., Wang et al implemented a traditional prime+probe attack which is more fine-grained and powerful on SGX-enabled platforms. (Sinharoy et al 2015). The functions of these subsystems include managing the boot process, keeping the system under thermal limits, and running based on user input modes and parameters.…”

“…On other hand, the complexity provides an attacker with a good chance to compromise the subsystem. On the other hand, the subsystem is implemented with embedded processors (Sinharoy et al 2015; Datenschutz and Pataky 2017; Advanced Micro Devices 2018b) which usually lack the common security hardening such as stack cookies, No-eXecute (NX) flags, or address space layout randomization (ASLR). Hence, there is also a security gap between the security requirements and the current security hardening.…”

The cache and memory subsystems of the IBM POWER8 processor

“…Beyond these foundational protocol improvements to single-thread and system-wide scaling for shared data and volatile-translation contexts, several hardware capabilities have been added to the cache hierarchy to directly enable high-value system software, middleware, and application features, as described in [8]. Such features include micro-partition prefetch and support for multiple concurrent partitions on a core, both of which enable higher performance for many smaller partitions, as well as the hardware-managed reference-history array to improve virtual-memory management.…”

Optimizing Sparse Linear Algebra for Large-Scale Graph Analytics

“…15 Each POWER8 core is equipped with private L1 and L2 caches of 64 Kbytes and 512 Kbytes, respectively. The L3 cache is shared, and each core has fast access to an 8-Mbyte slice.…”