Advanced interconnect challenges beyond 5nm and possible solutions

Park, K. C.; Simka, Harsono

doi:10.1109/iitc51362.2021.9537552

Cited by 9 publications

(7 citation statements)

References 8 publications

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“…In the context of interconnects, fabrication of high aspect ratio single crystal Cu nanostructures can greatly reduce resistivity by mitigating grain boundary scattering, [ 31 ] which currently limits further interconnect scaling via Damascene process. [ 32 ] For catalysis, increasing grain boundary density in nanostructures has been shown to increase catalytic activity compared to pristine surfaces. [ 33 ] For mechanical metamaterials such as nanolattices, nanocrystalline grain boundaries act as boundaries for dislocation motion, leading to enhanced strength and toughness.…”

Section: Discussionmentioning

confidence: 99%

Wafer‐Scale Fabrication of 2D Nanostructures via Thermomechanical Nanomolding

Kiani,

Sam,

Jung

et al. 2023

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With shrinking dimensions in integrated circuits, sensors, and functional devices, there is a pressing need to develop nanofabrication techniques with simultaneous control of morphology, microstructure, and material composition over wafer length scales. Current techniques are largely unable to meet all these conditions, suffering from poor control of morphology and defect structure or requiring extensive optimization or post‐processing to achieve desired nanostructures. Recently, thermomechanical nanomolding (TMNM) has been shown to yield single‐crystalline, high aspect ratio nanowires of metals, alloys, and intermetallics over wafer‐scale distances. Here, TMNM is extended for wafer‐scale fabrication of 2D nanostructures. Using In, Al, and Cu, nanomold nanoribbons with widths < 50 nm, depths ≈0.5–1 µm and lengths ≈7 mm into Si trenches at conditions compatible is successfully with back end of line processing . Through SEM cross‐section imaging and 4D‐STEM grain orientation maps, it is shown that the grain size of the bulk feedstock is transferred to the nanomolded structures up to and including single crystal Cu. Based on the retained microstructures of molded 2D Cu, the deformation mechanism during molding for 2D TMNM is discussed.

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Section: Discussionmentioning

confidence: 99%

Wafer‐Scale Fabrication of 2D Nanostructures via Thermomechanical Nanomolding

Kiani,

Sam,

Jung

et al. 2023

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“…Areas where the integration of epitaxial metals would lead to a significant breakthrough are for example, scaled interconnects [5,6], and emerging memories such * Author to whom any correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

Epitaxial growth of magnetron sputtered NiAl on Ge mediated by native GeOx

Ben Chroud,

Korytov,

Soulié

et al. 2024

J. Phys. D: Appl. Phys.

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In this work, the growth of a magnetron sputtered NiAl film on Ge was investigated. Two growth parameters were varied: the deposition temperature and the presence of native GeOx. An epitaxial layer was obtained at a deposition temperature of 400℃ and without removal of the native GeOx prior to deposition. At this growth condition, Ni and Al diffused into the Ge forming an epitaxial germanide. This germanide is most likely the τ3 phase of the Ni-Al-Ge ternary system. The growth of the τ3 phase is enabled by the GeOx acting as a diffusion barrier for Al. The native GeOx was found to be amorphous and to contain holes through which the NiAl can directly contact the τ3 germanide and grow epitaxially. These holes are likely formed by thermal degradation when the substrate is heated for deposition. The electrical resistivity for epitaxial NiAl was found to be 13 μΩ.cm at a thickness of 30 nm which was the lowest value of the tested conditions. Epitaxial NiAl can be used as a seed layer to grow other layers epitaxially in a CMOS-compatible process, e.g. Fe(Co), Cr, MgO, and Heusler alloys.

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“…Therefore, it is clear that improving metal interconnections is one of the main targets of modern research on electronics, given the electronics industry's significant economic and social impact. [38] To keep pace with the area reduction achieved in the front-end, the interconnect line width of the lowest layer of semiconductor devices becomes tighter down to 20 nm. This reduction in dimensions leads to significant multifaceted problems (Figure 1c).…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Materials Quest for Advanced Interconnect Metallization in Integrated Circuits

et al. 2023

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Integrated circuits (ICs) are challenged to deliver historically anticipated performance improvements while increasing the cost and complexity of the technology with each generation. Front‐end‐of‐line (FEOL) processes have provided various solutions to this predicament, whereas the back‐end‐of‐line (BEOL) processes have taken a step back. With continuous IC scaling, the speed of the entire chip has reached a point where its performance is determined by the performance of the interconnect that bridges billions of transistors and other devices. Consequently, the demand for advanced interconnect metallization rises again, and various aspects must be considered. This review explores the quest for new materials for successfully routing nanoscale interconnects. The challenges in the interconnect structures as physical dimensions shrink are first explored. Then, various problem‐solving options are considered based on the properties of materials. New materials are also introduced for barriers, such as 2D materials, self‐assembled molecular layers, high‐entropy alloys, and conductors, such as Co and Ru, intermetallic compounds, and MAX phases. The comprehensive discussion of each material includes state‐of‐the‐art studies ranging from the characteristics of materials by theoretical calculation to process applications to the current interconnect structures. This review intends to provide a materials‐based implementation strategy to bridge the gap between academia and industry.

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Advanced interconnect challenges beyond 5nm and possible solutions

Cited by 9 publications

References 8 publications

Wafer‐Scale Fabrication of 2D Nanostructures via Thermomechanical Nanomolding

Wafer‐Scale Fabrication of 2D Nanostructures via Thermomechanical Nanomolding

Epitaxial growth of magnetron sputtered NiAl on Ge mediated by native GeOx

Materials Quest for Advanced Interconnect Metallization in Integrated Circuits

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