Advanced mask process modeling for 45-nm and 32-nm nodes

Tejnil, Edita; Hu, Yi; Sahouria, Emile; Schulze, Steffen; Tian, Ming Jing; Guo, Eric

doi:10.1117/12.772975

Cited by 8 publications

(9 citation statements)

References 10 publications

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“…Recent work on mask process proximity modeling is enabling a departure from this paradigm. [35][36][37] This work involves calibrating a mask process model (MPC) based on mask CD or contour measurements, then referencing the MPC model to describe the mask input to the wafer OPC calibration flow. Figure 3 shows that a 50% reduction in mask CD variability can be realized with this approach.…”

Section: D and 2d Mask Effectsmentioning

confidence: 99%

Challenges for patterning process models applied to large scale

Sturtevant

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Full-chip patterning simulation has been utilized in semiconductor manufacturing for more than ten years, and has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasirigorous optical models and semiempirical resist and etch process models. There has been steady improvement in the predictive power and computational efficiency of the patterning models used in full chip simulation tools, and this paper will review this progress as well as the factors that ultimately limit the predictive capability of such models. In addition, this paper will outline the new process simulation challenges that are emerging as the industry approaches sub-0.25 k1 patterning. These challenges lie principally in improving accuracy and predictive capability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

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Section: D and 2d Mask Effectsmentioning

confidence: 99%

Challenges for patterning process models applied to large scale

Sturtevant

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…Prior work has established a framework to describe short-range etch effects in mask etch [13] and data processing methods for shape based correction [14,15]. In a previous publication a modeling flow capturing both long-range and short-range mask process effects was presented [1]. It described the generation of a customized test mask, mask measurements, and the generation of a long-range density and uniformity model along with a short-range mask process model.…”

Section: Introductionmentioning

confidence: 98%

“…Long range errors have been described in previous papers and are typically modeled with one or more Gaussian kernels [1]. Short-range errors are dominated primarily by etch processes.…”

Section: Introductionmentioning

confidence: 99%

Model based mask process correction and verification for advanced process nodes

2009

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The extension of optical lithography at 193nm wavelength to the 32nm node and beyond drives advanced resolution enhancement techniques that impose even tighter tolerance requirements on wafer lithography and etch as well as on mask manufacturing. The presence of residual errors in photomasks and the limitations of capturing those in process models for the wafer lithography have triggered development work for separately describing and correcting mask manufacturing effects. Long range effects -uniformity and pattern loading driven -and short range effects -proximity and linearity -contribute to the observed signatures. The dominating source of the short range errors is the etch process and hence it was captured with a variable etch bias model in the past [1]. The paper will discuss limitations and possible extensions to the approach for improved accuracy. The insertion of mask process correction into a post tapeout flow imposes strict requirements for runtime and data integrity. The paper describes a comprehensive approach for mask process correction including calibration and model building, model verification, mask data correction and mask data verification. Experimental data on runtime performance is presented. Flow scenarios as well as other applications of mask process correction for gaining operational efficiency in both tapeout and mask manufacturing are discussed.

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“…5 The mask in lithography is made by e-beam writing, and can be imperfect with significant errors on the critical dimension (CD), which can influence the intra-field CD uniformity on the final wafer. 6 The CD non-uniformity, which is the error between printed mask CD and target CD during the mask making process, can be caused by the e-beam exposure, the e-beam resist process and the etch process. Previous studies also show that the lens heating effect can cause mask shape deviation and best focus shift in the patterning process.…”

Section: Introductionmentioning

confidence: 99%

“…This concept has been proposed to integrate the photomask CD errors into an optical proximity correction (OPC) modeling and correction. 6 However, the extension to inverse lithography introduces new issue considering the large amount of pixel variables to optimize. The concept can also be considered as an extension of the mask error enhancement factor (MEEF) reduction, which is an objective in source mask optimization (SMO).…”

Section: Introductionmentioning

confidence: 99%

Incorporating photomask shape uncertainty in computational lithography

Liu

Erdmann

et al. 2016

SPIE Proceedings

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The lithographic performance of a photomask is sensitive to shape uncertainty caused by manufacturing and measurement errors. This work proposes incorporating the photomask shape uncertainty in computational lithography such as inverse lithography. The shape uncertainty of the photomask is quantitatively modeled as a random ?eld in a level-set method framework. With this, the shape uncertainty can be characterized by several parameters, making it computationally tractable to be incorporated in inverse lithography technique (ILT). Simulations are conducted to show the eâ¬ectiveness of using this method to represent various kinds of shape variations. It is also demonstrated that incorporating the shape variation in ILT can reduce the mask error enhancement factor (MEEF) values of the optimized patterns, and improve the robustness of imaging performance against mask shape ?uctuation

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Advanced mask process modeling for 45-nm and 32-nm nodes

Cited by 8 publications

References 10 publications

Challenges for patterning process models applied to large scale

Challenges for patterning process models applied to large scale

Model based mask process correction and verification for advanced process nodes

Incorporating photomask shape uncertainty in computational lithography

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