Advanced Package Technologies for High-Performance Systems

Power delivery, signaling and cooling for 2D and 3D integrated systems

“…Because the supply voltage decreases with each technology (although more slowly in the future) and decreasing timing margins, the allowable on-chip power supply noise will also decrease. However, the increase in power dissipation and the resulting increase in current drain of a SoC will increase the power supply noise and resistive losses through the motherboard, socket, package, and chip I/Os, which can become large [4,5,6]. In order to maintain acceptable on-chip supply noise, the number of power and ground pads must be scaled accordingly with each technology generation and appropriately sized on-chip wires and decoupling capacitors are allocated for the power distribution network [7].…”

Thermal Characterization of Thermal Interface Materials

“…This situation urges the development and characterization of all aspects of the thermal elements. Today the packaging technology for high power chips has moved to flip‐chip architectures with solder bump interconnections between the chip and the organic substrate 1 Figure 1. shows schematic diagrams of two flip‐chip architectures.…”

Detection of solder bump defects on a flip chip using vibration analysis

“…As the primary technology of electronic device packaging, surface mount technology (SMT) is correspondingly focused on small volume and high I/O density [1]. As a result of this development trend, flip chip packaging is introduced to SMT because of the advantage of small interconnection resistance and ultra-fine pitch [2].…”