Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

Marconi, S.; Orfanelli, S.; Hemperek, T.; Christiansen, J.; Placidi, P.

doi:10.1088/1748-0221/12/02/c02017

Cited by 8 publications

(3 citation statements)

References 8 publications

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“…The implementation is based on Shunt-LDO regulators integrated on the bottom of the chip. Two independent Shunt-LDO regulators [6], powered in parallel, provide independently the analog and digital supply voltages to the chip core with configurable input impedance (slope) and offset for optimal power dissipation and current sharing, as shown in Fig. 8 (left).…”

Section: Serial Poweringmentioning

confidence: 99%

Pixel detector for CMS upgrade

Orfanelli¹

2019

Proceedings of the 27th International Workshop on Vertex Detectors — PoS(VERTEX2018)

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The LHC machine upgrade program will increase the instantaneous luminosity delivered to the multi-purpose experiments up to 7.5x10 34 cm −2 s −1 in 2026, with the goal of an integrated luminosity of 3000 fb −1 by the end of 2037. In order to fully exploit this luminosity, CMS plans to build a completely new pixel detector. The Phase-2 pixel detector relies on highly radiation tolerant sensors and a new ASIC based on 65 nm CMOS technology. A high bandwidth readout system and a novel serial powering scheme of the pixel modules will be used to accommodate the highly demanding system needs. These prospective design choices as well as new layout geometries with acceptance extended from | η |< 2.4 to | η |< 4, will be presented along with some highlights of the R&D activities.

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Section: Serial Poweringmentioning

confidence: 99%

Pixel detector for CMS upgrade

Orfanelli¹

2019

Proceedings of the 27th International Workshop on Vertex Detectors — PoS(VERTEX2018)

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“…System simulations presented in [4] studied the SLDO performance in a serial power topology including the SLDO detailed design, decoupling capacitors, parasitics and dynamic power profiles of the chip's activity. These studies showed that thanks to the presence of multiple decoupling stages (off-chip decoupling capacitors, local decoupling of ∼300 nF for the digital and ∼70 nF for the analog part) and the isolation of the power domains, most of the fast current variations would be absorbed and the noise coupling between the two power domains would be within acceptable levels 1 .…”

Section: An Improved Shunt-ldo Regulatormentioning

confidence: 99%

Serial Powering Optimization for CMS and ATLAS Pixel Detectors within RD53 Collaboration for HL-LHC: System Level Simulations and Testing

Orfanelli¹,

Hinterkeuser²,

Ruini³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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ETHZSerial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. Two 2.0 A Shunt-LDO regulators are integrated in a prototype pixel chip implemented in 65-nm CMOS technology and used to provide constant supply voltages to its power domains from a constant input current. Performance results from testing prototype Shunt-LDO regulators are shown, including their behaviour after x-ray irradiation. The system level simulation studies, which had been performed with a detailed regulator design in a serially powered topology, have been validated.

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“…This paper presents three ways we have profited from the environment for different purposes: evaluating the performance of digital architectures, addressing their optimization for the implementation on the RD53A chip and performing extensive functional verification. It should be mentioned that the environment was also used for performing power profiling in order to verify serial powering operation [6]. This paper is organized as follows: section 2 describes the VEPIX53 simulation environment and its most relevant verification components.…”

Section: Introductionmentioning

confidence: 99%

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

et al. 2018

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The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted. K: Digital electronic circuits; Front-end electronics for detector readout; Pixelated detectors and associated VLSI electronics; Simulation methods and programs 1Corresponding author.

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Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

Cited by 8 publications

References 8 publications

Pixel detector for CMS upgrade

Pixel detector for CMS upgrade

Serial Powering Optimization for CMS and ATLAS Pixel Detectors within RD53 Collaboration for HL-LHC: System Level Simulations and Testing

A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

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