Advanced Reliability Modeling of Cu/low-k Interconnection in FCBGA Package

Fioriam, V.; Zhang, Xueren; Tee, Tong Yan

doi:10.1109/ectc.2006.1645771

Cited by 14 publications

(6 citation statements)

References 12 publications

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“…Until now, submodeling was shown for copper interconnects [9], [10], solder bumps [11], and interlayer dielectric cracking in flip chip assemblies [12]. In this paper, it will be demonstrated that homogenization combined with two-level submodeling is already sufficient to accurately model degradation in the on-chip metallization of LDMOS transistors.…”

Section: Introductionmentioning

confidence: 95%

“…Another approach to reduce meshing effort and thus simulation time is to substitute regions that require a very dense mesh (for instance the many metal fingers of the LDMOS with the vias and contacts) by an equivalent layer consisting of a single homogeneous material, e.g., as described in [6]- [9]. This results in much easier meshing, however, simulation accuracy is lower because the structure of the substituted regions is lost.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Simulation of Thermo-Mechanical Stress in the On-Chip Metallization of Integrated Power Semiconductors

Pham

Ritter

Pfost

2017

IEEE Trans. Device Mater. Relib.

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Integrated power semiconductors are often used for applications with cyclic on-chip power dissipation. This leads to repetitive self-heating and thermo-mechanical stress, causing fatigue on the on-chip metallization and possibly destruction by short circuits. Because of this, an accurate simulation of the thermo-mechanical stress is needed already during the design phase to ensure that lifetime requirements are met. However, a detailed thermo-mechanical simulation of the device, including the on-chip metallization is prohibitively time-consuming due to its complex structure, typically consisting of many thin metal lines with thousands of vias. This paper introduces a two-step approach as a solution for this problem. First, a simplified but fast simulation is performed to identify the device parts with the highest stress. After, precise simulations are carried out only for them. The applicability of this method is verified experimentally for LDMOS transistors with different metal configurations. The measured lifetimes and failure locations correlate well with the simulations. Moreover, a strong influence of the layout of the on-chip metallization lifetime was observed. This could also be explained with the simulation method. Index Terms-Integrated power technologies, integrated circuit modeling, power semiconductor devices, on-chip metallization, thermo-mechanical stress, degradation, reliability.

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Section: Introductionmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

Efficient Simulation of Thermo-Mechanical Stress in the On-Chip Metallization of Integrated Power Semiconductors

Pham

Ritter

Pfost

2017

IEEE Trans. Device Mater. Relib.

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“…For efficient numerical analysis (minimized CPU time and RAM requirements) of thermo-mechanical processes in power ICs, multi-scale FEM was recently used [13]- [17]. The main advantage of multi-scale FEM is the progressive reduction of the computational domain towards the presumed failure region.…”

Section: Introductionmentioning

confidence: 99%

“…The multi-scale FEM is based on the cut-boundary method, which assumes that displacement results from the macro-scale model are used to constrain the lower-scale models [15]. Although the multi-scale FEM is widely used in the thermomechanical analysis of power IC, strong limitations can occur because the simulation results are transferred only in one-wayfrom the macro to micro-scale sub-models [13]- [17]. Hence, in case of time-dependent problems, such as the local plasticity of the IC metallization system, because the micro sub-models contributions (e.g.…”

Section: Introductionmentioning

confidence: 99%

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

Bojita

Purcar

Simon

et al. 2022

IEEE J. Electron Devices Soc.

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During development of power IntegratedCircuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. 10 4 -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions -the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time -and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.

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“…A system in package contains many components such as function die, crystal, capacities and resistance, etc. The reliability problem for a SiP unit is caused by the mismatch of thermal expansion coefficients among packaging materials and devices which can lead to warping or delaminating in the package [4][5][6][7][8][9][10][11]. In the real product line, a few units are assembled together on a PCB sheet so as to increase the productivity significantly.…”

Section: Introductionmentioning

confidence: 99%

Warpage control of wireless LAN SiP during manufacturing process

Gao

Hong

Hyun

et al. 2007

2007 International Conference on Electronic Materials and Packaging

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In this study, the warpage of WLAN strip after reflow process, which contains 7x5 WLAN modules, is considered. 3D thermo-mechanical FEM simulation is carried out to find out the warpage distribution and maximum warpage after reflow process. Experimental investigation on the warpage measurement of the package is also performed to verify the simulation results. Furthermore, some new designs on the manufacturing of the module strip, such as reducing the density of module or cutting grooves on the PCB, adding extra pins on the carrier, are proposed and compared with the currently used one. The results show that pin carrier is an effective way to reduce the warpage. The more pins on the carrier, the more efficient in reducing the warpage. Decreasing the unit density on the PCB or cutting grooves in the PCB are also ways to reduce the warpage. The less units on a single PCB sheet, the smaller the warpage. The most effective method to reduce strip warpage is to add a central pin on the PCB which can help control the maximum warpage to be within 50μm.

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Advanced Reliability Modeling of Cu/low-k Interconnection in FCBGA Package

Cited by 14 publications

References 12 publications

Efficient Simulation of Thermo-Mechanical Stress in the On-Chip Metallization of Integrated Power Semiconductors

Efficient Simulation of Thermo-Mechanical Stress in the On-Chip Metallization of Integrated Power Semiconductors

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

Warpage control of wireless LAN SiP during manufacturing process

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