2017 IEEE International Electron Devices Meeting (IEDM) 2017
DOI: 10.1109/iedm.2017.8268493
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Advanced silicon photonics technology platform leveraging a semiconductor supply chain

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Cited by 26 publications
(21 citation statements)
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“…Due to the potential compatibility of silicon photonics with the well-established industrialization methodologies used in CMOS technologies, there has been a significant thrust for monolithic integration of silicon photonics with electronics [85]. The additional parasitic capacitance and inductance of wirebonds or micro-bumps used by the hybrid electronic-photonic integrated circuit (EPIC) platforms [86]- [89] is minimized by Front-end-of-line (FEOL) integration of photonic components with electronics [30], [90]. Monolithic EPICs have a potential to meet the stringent power dissipation and aggregate throughput demands for short-to-long-range photonic interconnects [30], [44], [90].…”
Section: B Monolithic Silicon Photonics-electronics Co-integrationmentioning
confidence: 99%
“…Due to the potential compatibility of silicon photonics with the well-established industrialization methodologies used in CMOS technologies, there has been a significant thrust for monolithic integration of silicon photonics with electronics [85]. The additional parasitic capacitance and inductance of wirebonds or micro-bumps used by the hybrid electronic-photonic integrated circuit (EPIC) platforms [86]- [89] is minimized by Front-end-of-line (FEOL) integration of photonic components with electronics [30], [90]. Monolithic EPICs have a potential to meet the stringent power dissipation and aggregate throughput demands for short-to-long-range photonic interconnects [30], [44], [90].…”
Section: B Monolithic Silicon Photonics-electronics Co-integrationmentioning
confidence: 99%
“…Flip-chip packaging capability is required for high-performance applications such as 400G optical transceivers, mid-board modules and co-packaging with the SoC. Solving this problem demands the development of silicon photonics platform with TSVs [5].…”
Section: Nmos F T (Ghz)mentioning
confidence: 99%
“…The issues with limited transistor performance and process qualification/availability recently have taken the manufacturers in a different direction. Both STMicroelectronics and TSMC have demonstrated hybrid integration of CMOS with Luxtera's photonic technology implemented in standalone photonic SOI wafers [5,6]. This approach decouples the transistor process development from the photonic process development and is seemingly very attractive since it allows the latest node CMOS circuitry to be used in conjunction with optimized photonic devices.…”
Section: Introductionmentioning
confidence: 99%
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“…In some cases, CMOS pilot lines provide low-and medium-volume manufacturing of silicon PICs, typically up to several hundred wafers per order. With the growing industrial interest in high-volume manufacturing of silicon photonics products for telecommunication/datacommunication applications, which is the biggest driver for this technology since its inception, pure-play fabs have started developing open-access silicon photonics technologies [21]. In certain cases, the CMOS pilot lines and research institutes partner with pure-play CMOS fabs for the seamless translation from prototyping towards high-volume manufacturing [22].…”
Section: Introductionmentioning
confidence: 99%