Advanced Source/Drain Engineering for MOSFETs: Schottky Barrier Height Tuning for Contact Resistance Reduction

Yeo, Yee-Chia

doi:10.1149/1.3375592

Cited by 7 publications

(1 citation statement)

References 13 publications

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“…For automotive applications, operations in a wide range of temperatures must be guaranteed. At low voltages and low temperatures, however, the contact resistances (R C ) of the transistors rise rapidly [1]. In conjunction with the additional increase due to device scaling, this is one of the main difficulties in the automotive and mobile applications of DRAMs.…”

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confidence: 99%

The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

et al. 2022

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In this work we report on the improvement in cold temperature characteristics of PMOSFETs and inverter circuits by removing the plasma-damaged layer of the source/drain contacts. We removed the plasma-induced damage on the Si using a simple in situ Si soft treatment technique. We found by transmission electron microscope (TEM) analysis that the damaged amorphous layer reduced from 52 Å to 42 Å and 35 Å with a treatment time of 10 and 20 s, respectively. As a result, the resistances of both the n+ and p+ contacts decreased for all contact sizes and the standard deviations at the cold temperature were suppressed by 45%. At −25 °C, the saturation current of the PMOSFET increased by 3% and the propagation delay time (tPD) decreased by 2%. The tPD increases by 19.3% when the temperature decreases from 85 °C to −25 °C, and the operating voltage decreases from 1.2 V to 0.95 V at the same time. However, this increase can be reduced to 17% by applying the soft treatment for 10 s. This simple and short time process will be considered essential for both mobile applications and automotive applications of dynamic random access memory (DRAM) devices requiring a low-voltage and low-temperature operation.

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Section: Introductionmentioning

confidence: 99%

The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

et al. 2022

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Investigation of ultrathin yttrium silicide for NMOS source/drain contacts

Sun

Gao

et al. 2023

J Mater Sci: Mater Electron

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Effective Schottky barrier lowering of Ni silicide/p-Si(100) using an ytterbium confinement structure for high performance n-type MOSFETs

et al. 2017

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Effective Schottky barrier lowering of Ni silicide/p-Si(100) using an ytterbium confinement structure for high performance n-type MOSFETs Author links open overlay panelKeng-HuiShen a Szu-HungChen b Wei-TingLiu a Bao-HsienWu a Lih-JuannChen a Show more https://doi.org/10.1016/j.matdes.2016.11.084 Get rights and content Highlights • The insertion of Ti layer effectively suppresses Yb out-diffusion and prevents the Yb from oxidation during silicidation. • Yb atoms are confined by the inserted Ti layer and react with both Ni and Si to form Yb-Ni silicide. • The confinement leads the SBH of the system to a 0.02 and 0.025 eV lowering at 500 and 600 °C, respectively. • The RE metal confinement structure provides a CMOS compatible approach for further SBH engineering and technology nodes. Abstract A simple but effective rare earth metal (RE) confinement structure is demonstrated to suppress surface accumulation of Yb generally encountered in the RE metal incorporated Ni silicide system. The confinement structure is realized by inserting a Ti diffusion barrier layer between Yb and Ni layers. Yb atoms can be constrained in a specified reaction region during silicidation as evidenced by Auger electron spectroscopy and cross-section transmission electron microscopy analysis. The RE metal confinement structure provides a complementary metal-oxide-semiconductor compatible approach for further Schottky barrierheight engineering and is a promising method for future technology nodes. Graphical abstract 1. Download high-res image (272KB) 2. Download full-size image 

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Advanced Source/Drain Engineering for MOSFETs: Schottky Barrier Height Tuning for Contact Resistance Reduction

Cited by 7 publications

References 13 publications

The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

Investigation of ultrathin yttrium silicide for NMOS source/drain contacts

Effective Schottky barrier lowering of Ni silicide/p-Si(100) using an ytterbium confinement structure for high performance n-type MOSFETs

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