Advanced Substrate Packaging Technologies for Enabling Heterogeneous Integration (HI) Applications

EMIB and advanced substrate packaging technologies to enable heterogeneous integration (HI) applications

“…Advanced substrates will be a key enabler for chiplet HI. 28) Significantly disruptive substrate packaging technologies must be developed to address the upcoming challenges to meet rising AI and HPC demands.…”

“…Recently a MCP created for the DARPA CHIPS Common HI and IP Reuse Strategies was used to validate a multi-pitch 55/36 μm EMIB package together with mixed FLI bumping surface finishes. 17,24) The CHIPS program goal is to use chiplets from different Si nodes and foundries, connected using a common interface as building blocks to create complex systems and to demonstrate effective HI. As part of the CHIPS program, Intel is collaborating in creating multichip prototypes that can integrate chiplets of many kinds.…”

“…Embedded multi-interconnect bridge (EMIB) technology is an advanced, cost-effective approach to deliver localized high density on-package interconnects for individually optimized links between heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths among multiple dice in the same package. [13][14][15][16][17] EMIB allows a significant level of design flexibility in the placement of heterogeneous dice and mixing of components to optimize system level performance. It is compatible with different Si technology nodes and enables large form factor (FF) die stitching capability with a high number of bridges embedded in the package substrate.…”

A Low-Cost Passivation for Low Temperature Cu-Cu Bonding Using PVD-Deposited Cu3N

“…Advanced package technologies offer an alternative path from transistor scaling to enhance the performance of electron devices. As a result, numerous institutes and companies have engaged in this field, including EMIB from Intel [1], [2], SoIC from TSMC [3], [4], and etc. In advanced package schematics, the transmission distance of signal and power among functional chiplets could be significantly reduced.…”