Advanced TCAD Simulation of Tunnel Oxide Degradation for EEPROM Applications

Abstract

In this paper we have simulated dynamic Constant Voltage Stress (CVS) and subsequent degradation of MOS capacitor representative of Non-Volatile Memory (NVM) devices. Oxide degradation was modelled through trap defects generation at SiO2/Si interface and SiO2 bulk. A very good agreement was obtained between simulation and experimental data.