Advanced timing analysis based on post-OPC extraction of critical dimensions

Abstract

While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the layout introducing systematic variations to the simulated and verified performance. As a result, actual on-silicon chip performance is quite different from sign-off expectations. This paper presents a new methodology to provide better estimates of on-silicon performance. The technique relies on the extraction of residual OPC errors from placed and routed full chip layouts to derive actual (i.e., calibrated to silicon) CD values that are then used in timing analysis and speed path characterization. This approach is applied to a state-of-theart microprocessor and contrasted with traditional design flow practices where ideal (i.e., drawn) Lgate values are employed, leading to a subsequent lack of predictive power. We present a platform for diagnosing and improving OPC quality on gates with specific functionality such as critical gates or matching transistors. Furthermore, with more accurate timing analysis we highlight the necessity of a post-OPC verification embedded design flow, by showing substantial differences in the Si-based timing simulations in terms of significant reordering of speed path criticality and a 36.4% increase in worst-case slack. Extensions of this methodology to multi-layer extraction and timing characterization are also proposed.

Impact of Guardband Reduction On Design Outcomes: A Quantitative Approach

“…Gupta et al [11] observe that lithography simulation permits post-OPC (optical proximity correction) estimation of on-silicon feature sizes at different process conditions. Yang et al [24] address post-lithography based analysis and optimization, proposing a timing analysis flow based on residual OPC errors (equivalent to lithography simulation output) for timing-critical cells and their layout neighborhoods. Cao et al [8] propose a methodology for standard-cell characterization consid- ering litho-induced systematic variations.…”

“…And, what is the specific return that we can expect to be realized by the design team from availability of, e.g., iso-dense aware timing analysis [10], post-lithography based analysis and optimization [24], or any other potential path to reduced guardband? The following sections describe our efforts toward a quantified answer to this question.…”

Statistical timing analysis based on simulation of lithographic process

“…A recently proposed work addressed the post lithography analysis and optimization by proposing a timing flow based on residual OPC errors [15]. They consider only timing critical cells and do not take into account that the proximity effects are seen throughout the die.…”

Standard cell characterization considering lithography induced variations

“…A pioneer work [3] tried to estimate gate length variations through computationally expensive aerial image process simulations. Recently, a post OPC extraction methodology was proposed [4] for timing analysis of critical paths in a design with expensive litho simulation and complicated timing characterization scheme. Another work [5] proposed a timing analysis methodology with awareness of lithography induced gate length variations according to different poly pitches.…”