Advanced transistor structures for high performance microprocessors

Horstmann, Μ.; Greenlaw, D.; Feudel, Thomas; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, Matthias; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, Μ.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, Ralf van; Graßhoff, G.; Schwan, C.; Cheek, J.; Buller, J.F.; Krishnan, S.; Raab, M.; Kepler, N.

doi:10.1109/icicdt.2004.1309909

Cited by 3 publications

(2 citation statements)

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“…A variety of spacer structures can be used between multiple implant processes to tailor the S/D junction to maximize drive current while maintaining low parasitic capacitance of the transistor. 1 As shown in Figure 2, the first offset spacer is formed before (pMOS) or after (nMOS) the lightly doped SDE junctions are formed, but before halo implants are put in the channel. Then second and third nitride spacers are formed for heavier buffer and S/D implants, respectively.…”

Section: Spacer Profile Controlmentioning

confidence: 99%

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Advanced 3D-AFM Metrology for Sidewall Spacers

2009

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Gate spacer engineering has become one of the primary concerns in dimensional metrology for semiconductor manufacturing process control. In composite spacers, deposition and etch of each spacer determine where the transistor source/drain implants occur. The sidewall spacer thickness and profile, especially at the feature bottom, is critical to be characterized and controlled by applicable 3D metrology. This paper discusses recent advances in 3D atomic force microscopy (3D-AFM) that solve the specialized characterization needs for critical sidewall spacer geometry controls, including multiple spacer thickness and nitride spacer pulldown. 3D-AFM metrology measures with greater accuracy such typical gate spacer parameters as linewidth, height, pitch, sidewall profile, sidewall angle (SWA), line edge roughness (LER), and line width variation (LWV), and sidewall roughness (SWR).

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Section: Spacer Profile Controlmentioning

confidence: 99%

“…For example, 25% improvement of pMOS saturation drain-current has been achieved with the triple spacer transistor design over the single spacer structure. 1 Unfortunately, transistor electrical performance is evaluated only when the first interconnect is completed. This happens weeks after implant processing.…”

Section: Spacer Profile Controlmentioning

confidence: 99%