Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling

Pigorsch, Florian; Scholl, Christoph; Disch, Stefan

doi:10.1109/fmcad.2006.4

Cited by 17 publications

(27 citation statements)

References 24 publications

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“…Sequential equivalence checking has been one of the most challenging tasks in EDA during the last decades [19], [20]. In order to prove functional equivalence of two systems in a worst-case scenario, it is required to generate and compare a complete representation of the state space of both systems, which is known to be exponential with respect to number of memory elements contained in the systems.…”

Section: Verification and Validationmentioning

confidence: 99%

Design, Verification, and Application of IEEE 1687

Zadegan

Larsson

Jutman³

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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Abstract-IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

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Section: Verification and Validationmentioning

confidence: 99%

Design, Verification, and Application of IEEE 1687

Zadegan

Larsson

Jutman³

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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“…LinAIGs consist of both a boolean and a continuous part. The boolean part of LinAIGs is represented by functionally reduced AndInverter-Graphs (FRAIGs) [17,20], which basically are boolean circuits consisting only of and gates and inverters. In order to represent the continuous part, LinAIGs use a set of boolean constraint variables Q where each linear constraint is encoded by some q l ∈ Q.…”

Section: Model Checking Algorithmmentioning

confidence: 99%

Fully Symbolic Model Checking for Timed Automata

Morbé

Pigorsch

Scholl

2011

Computer Aided Verification

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Abstract. In this paper we introduce a new formal model, called finite state machines with time (FSMT), to represent real-time systems. We present a model checking algorithm for FSMTs, which works on fully symbolic state sets containing both the clock values and the state variables. In order to verify timed automata (TAs) with our model checking algorithm, we present two different methods to convert TAs to FSMTs. In addition to pure interleaving semantics we can convert TAs to FSMTs having a parallelized interleaving behavior which allows parallelism of transitions causing no conflicts. This can dramatically reduce the number of steps during verification. Our experimental results show that our prototype implementation outperforms the state-of-the-art model checkers UPPAAL and RED.

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“…As presented in [23] the original AIGSolve would then transform the QBF into an AIG representation and eliminate all quantifiers in a bottom-up fashion by performing cofactoring on AIG cones (similar to the BED-based approach in [1]), compressing the individual results of quantifier elimination by BDD-sweeping [24], functional reduction [20] and DAG-aware rewriting [19] of the AIG structure.…”

Section: Aig-based Solving With Bdd Supportmentioning

confidence: 99%

An AIG-Based QBF-solver using SAT for preprocessing

Pigorsch

Scholl

2010

Proceedings of the 47th Design Automation Conference

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In this paper we present a solver for Quantified Boolean Formulas (QBFs) which is based on And-Inverter Graphs (AIGs). We use a new quantifier elimination method for AIGs, which heuristically combines cofactor-based quantifier elimination with quantification using BDDs and thus benefits from the strengths of both data structures. Moreover, we present a novel SAT-based method for preprocessing QBFs that is able to efficiently detect variables with forced truth assignments, allowing for an elimination of these variables from the input formula. We describe the used algorithm which heavily relies on the incremental features of modern SATsolvers. Experimental results demonstrate that our preprocessing method can significantly improve the performance of QBF preprocessing and thus is able to accelerate the overall solving process when used in combination with state-of-the-art QBF-solvers. In particular, we integrated the preprocessing technique as well as the quantifier elimination method into the QBF-solver AIGSolve, allowing it to outperform state-of-the-art solvers.

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Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling

Cited by 17 publications

References 24 publications

Design, Verification, and Application of IEEE 1687

Design, Verification, and Application of IEEE 1687

Fully Symbolic Model Checking for Timed Automata

An AIG-Based QBF-solver using SAT for preprocessing

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