Advanced verification by automatic property generation

Rogin, Frank; Klotz, Thomas; Fey, Görschwin; Drechsler, Rolf; Rulke, S.

doi:10.1049/iet-cdt.2008.0110

Cited by 10 publications

(5 citation statements)

References 14 publications

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“…Designer-guided approaches [32], [33] require manual effort. Automatic generation of properties is usually incomplete and depends on abstract design descriptions [34] or models [35], or analysis of simulation traces [36], which may be difficult. In contrast, we have general completeness results for A-QED 2 .…”

Section: Related Workmentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique which uses Bounded Model Checking for pre-silicon verification of HAs. A-QED checks an HA for self-consistency, i.e., whether identical inputs within a sequence of operations always produce the same output. Under modest assumptions, A-QED is both sound and complete. However, as is well-known, large design sizes significantly limit the scalability of formal verification, including A-QED. We overcome this scalability challenge through a new decomposition technique for A-QED, called A-QED with Decomposition (A-QED 2 ). A-QED 2 systematically decomposes an HA into smaller, functional sub-modules, called sub-accelerators, which are then verified independently using A-QED. We prove completeness of A-QED 2 ; in particular, if the full HA under verification contains a bug, then A-QED 2 ensures detection of that bug during A-QED verification of the corresponding subaccelerators. Results on over 100 (buggy) versions of a wide variety of HAs with millions of logic gates demonstrate the effectiveness and practicality of A-QED 2 . This article will appear in the proceedings of Formal Methods in Computer-Aided Design (FMCAD 2021).

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Section: Related Workmentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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“…Regarding properties, another area of future work is to consider how to extract properties automatically from the binary (or source code). There is some existing work in this area [34], [35] although they focus upon high level behaviour rather than binary code.…”

Section: A Future Workmentioning

confidence: 99%

An Automated Formal Process for Detecting Fault Injection Vulnerabilities in Binaries and Case Study on PRESENT

Given-Wilson

Jafri

Lanet

et al. 2017

2017 IEEE Trustcom/BigDataSE/Icess

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Recently fault injection has increasingly been used both to attack software applications, and to test system robustness. Detecting fault injection vulnerabilities has been approached with a variety of different but limited methods. This paper proposes a general process without these limitations that uses model checking to detect fault injection vulnerabilities in binaries. The efficacy of this process is demonstrated by detecting vulnerabilities in the PRESENT binary.

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“…For example, Minmin [11] used StateCharts to formally model adaptive Web application navigations and shown how important properties of navigation model were verified. Rogin [12] proposed a new methodology to automatically generate complex properties for a given design, which described the abstract design behavior and improved design understanding. Hu [13] proposed a new general approach to property verification for access control models.…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach to Generate the Property for Web Service Verification from Threat-Driven Model

Zhu¹,

Gao²

2014

Appl. Math. Inf. Sci.

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Web service is considered as one of the most promising computing paradigms, which works as plugin mode to provide the value-added applications in Service-Oriented Computing (SOC) and Service-Oriented Architecture (SOA). The general Web service verification focuses on functionality and its termination, such as deadlock or livelock. However, it might not be able to help in accurately understanding service behaviours because it lacks interaction verifications, especially temporal behaviours. To this point, automatically generating proper temporal logic formulae of verification property is a primary and important task since the manual property generation is time-consuming and error-prone. Thus, this paper proposes an approach extending UML as service threat-driven model to generate the verification property, including the features of functionality, time constraints and probability during service interactions. First, it introduces a scenario description tool, mainly Probabilistic Timed Live Sequence Chart (PTLSC), on which kinds of implication threats are discussed, specifying the insecure behaviours which should be prohibited from occurring in Web service. Second, it gives corresponding transformation methods to extract the verification property from threat-driven model, in which the message coverage criterion and partial relation are employed. These formulae are in the form of Probabilistic Timed Computation Tree Logic (PTCTL), which afford an underlying guideline to guarantee the correctness and reliability of Web service since its threat-carried characteristics.

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Advanced verification by automatic property generation

Cited by 10 publications

References 14 publications

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

An Automated Formal Process for Detecting Fault Injection Vulnerabilities in Binaries and Case Study on PRESENT

A Novel Approach to Generate the Property for Web Service Verification from Threat-Driven Model

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