Advances in process overlay

Hinnen, Paul; Megens, Henry; Schaar, Maurits van der; Haren, Richard J. F. van; Mos, E.C.; Lalbahadoersing, S.; Bornebroek, Frank; Laidler, David

doi:10.1117/12.436734

Cited by 6 publications

(3 citation statements)

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“…The remaining offsets at zero period are attributed to Al-PVD effects. It is well known that Al-PVD causes spurious wafer expansion and wafer rotation effects, as described before [7,8].…”

Section: Predictive Recipes On Vspmsmentioning

confidence: 97%

Overlay performance with advanced ATHENA alignment strategies

et al. 2003

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After the introduction of the ATHENA TM alignment sensor, advanced applications of the sensor data are becoming increasingly important to meet the tightening overlay specifications for future technology nodes. As part of the total overlay budget, the effects of different alignment strategies on overlay performance need to be investigated. Keeping in mind that such strategies are simple and easy to use, two developments are addressed in this paper: advanced alignment recipes and advanced mark designs.An alignment recipe defines which signals from the sensor are used to calculate the aligned position. By making advanced use of the available data, wafer alignment can be made more accurate and more robust to processing effects. It is shown that the new Smooth Color Dynamic alignment recipes exhibit good overlay performance on STI, Cu dual damascene and W-CMP / Al-PVD layers. Since Smooth Color Dynamic also takes away the choice of a particular color in the alignment recipe, it is the preferred alignment recipe for all product layers.The optimum design of an alignment mark depends on the process characteristics. As the process characteristics may vary over time, the optimum mark design can change accordingly. To cover a larger process range, multiple alignment mark designs are combined in a new multi-grating mark: the Versatile Scribeline Primary Mark (VSPM). By measuring all gratings during regular production, the optimum grating of a VSPM can be selected and aligned with a Smooth Color Dynamic alignment recipe. For CMP layers a further overlay improvement can be achieved if all gratings have comparable phase depths. By combining alignment signals from different gratings in a predictive alignment recipe, wafer-to-wafer variations due to CMP effects can be reduced.

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“…The remaining offsets at zero period are attributed to Al-PVD effects. It is well known that Al-PVD causes spurious wafer expansion and wafer rotation effects, as described before [7,8].…”

Section: Predictive Recipes On Vspmsmentioning

confidence: 97%

Overlay performance with advanced ATHENA alignment strategies

et al. 2003

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“…5 To evaluate the effects of mark filling, experimental splits with increased tungsten thickness and reduced oxide thickness were used to increase the mark filling and create different mark topography compared to the nominal process.…”

Section: Mark Fillingmentioning

confidence: 99%

Advances in process overlay: ATHENA alignment system performance on critical process layers

et al. 2002

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The continuing reduction of IC device dimensions puts stringent demands on the corresponding overlay performance. As part of the total overlay budget, the effects of the different process parameters need to be characterized and well understood. In a joint development program between IMEC and ASML, the robustness of different alignment strategies to process parameters has been evaluated using the ATHENA alignment system. This paper looks at both Front-end (Shallow Trench Isolation) and Back-end (W-CMP and copper dual damascene) processing.To investigate the effect of STI processing on alignment marks in Front-end processing an extensive evaluation has been performed in which both mark design and process parameters have been varied. The robustness to typical long term process variation at the STI CMP step in a production environment has also been evaluated.To improve the robustness of alignment marks in Back-end processing, new mark designs have been evaluated. These designs have been evaluated for two different processes. The first uses traditional W-CMP and sputtered aluminum. The second uses copper dual damascene, with layer stacks consisting of both conventional and low-k dielectric materials. This knowledge will be used to generate alignment strategies for future technology nodes.

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“…In phased introductions, sensor and applications improvements were validated and integrated in production environments, at various customer sites [2,7,9,10,11,13,14,16]. With the knowledge gained from joint development activities on on-product overlay, the increasing importance of synchronizing alignment mark design criteria, with alignment sensor hardware specifics was recognized [3,4,5,6]. Significant steps forward in this field were made, operating within the boundaries of the ATHENA TM sensor [4,6,8,15].…”

Section: Introductionmentioning

confidence: 99%

Integration of a new alignment sensor for advanced technology nodes

Hinnen

Depre²,

Tanaka³

et al. 2007

SPIE Proceedings

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In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensor's infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

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Advances in process overlay

Cited by 6 publications

References 0 publications

Overlay performance with advanced ATHENA alignment strategies

Overlay performance with advanced ATHENA alignment strategies

Advances in process overlay: ATHENA alignment system performance on critical process layers

Integration of a new alignment sensor for advanced technology nodes

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