Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Patnaik, Satwik; Rangarajan, Nikhil; Knechtel, Johann; Sinanoglu, Ozgur; Rakheja, Shaloo

doi:10.23919/date.2018.8341986

Cited by 44 publications

(31 citation statements)

References 37 publications

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“…The gates' functionalities are not static anymore, possibly even for static input patterns, whereupon an attacker is bound to misinterpret some parts of the layout-it seems impossible to resolve all dynamic features on a full-chip scale at once. 1 Besides hindering read-out threats, polymorphism at the system level is also powerful to thwart SAT attacks. In fact, we provide such a concept based on the GSHE switch in Sec.…”

Section: ) Layout Identification and Read-out Attacksmentioning

confidence: 99%

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Patnaik

Rangarajan

Knechtel³

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Protecting intellectual property (IP) has become a serious challenge for chip designers. Most countermeasures are tailored for CMOS integration and tend to incur excessive overheads, resulting from additional circuitry or device-level modifications. On the other hand, power density is a critical concern for sub-50 nm nodes, necessitating alternate design concepts. Although initially tailored for error-tolerant applications, imprecise computing has gained traction as a general-purpose design technique. Emerging devices are currently being explored to implement ultra-low-power circuits for inexact computing applications. In this paper, we quantify the security threats of imprecise computing using emerging devices. More specifically, we leverage the innate polymorphism and tunable stochastic behavior of spin-orbit torque (SOT) devices, particularly, the giant spin-Hall effect (GSHE) switch. We enable IP protection (by means of logic locking and camouflaging) simultaneously for deterministic and probabilistic computing, directly at the GSHE device level. We conduct a comprehensive security analysis using state-of-the-art Boolean satisfiability (SAT) attacks; this study demonstrates the superior resilience of our GSHE primitive when tailored for deterministic computing. We also demonstrate how probabilistic computing can thwart most, if not all, existing SAT attacks. Based on this finding, we propose an attack scheme called probabilistic SAT (PSAT) which can bypass the defense offered by logic locking and camouflaging for imprecise computing schemes. Further, we illustrate how careful application of our GSHE primitive can remain secure even on the application of the PSAT attack. Finally, we also discuss side-channel attacks and invasive monitoring, which are arguably even more concerning threats than SAT attacks.

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Section: ) Layout Identification and Read-out Attacksmentioning

confidence: 99%

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Patnaik

Rangarajan

Knechtel³

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…By tying the bits of an OTP or encryption pulse to the control bit of a CNOT gate, one can achieve controlled inversion of bits in the plaintext, depending on the encryption pulse. Spin devices like the ME-AFM transistor [42] are able to implement polymorphic logic gates, which can achieve inverting or non-inverting functionality based on a control signal [43]. Hence, the ME-AFM transistor can directly realize the CNOT gate.…”

Section: Data Con Dentiality Attacksmentioning

confidence: 99%

SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory

et al. 2020

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Data the and tampering are serious concerns as a ackers have aggressively begun to exploit weaknesses in current memory systems to advance their nefarious schemes. e storage industry is moving toward emerging non-volatile memories (NVM), including the spin-transfer torque magnetoresistive random access memory (STT-MRAM) and the phase change memory (PCM), owing to their high density and low power operation. e advent of novel memory technologies has led to new vulnerabilities including data sensitivity to magnetic eld and temperature uctuations and data persistence a er power down. In this paper, we propose SMART: a Secure Magnetoelectric Antiferromagnet-Based Tamper-Proof memory, which leverages unique properties of antiferromagnetic materials and offers dense, on-chip non-volatile storage. SMART memory is not only resilient against data con dentiality a acks seeking to leak sensitive information but also protects data integrity and prevents Denial of Service (DoS) a acks on the memory. It is impervious to power side-channel a acks, which exploit asymmetric reads/writes for '0' and '1' logic levels, and photonic side-channel a acks, which monitor photo-emission signatures from the chip backside. Further, the ultra-low power magnetoelectric switching coupled with the terahertz regime antiferromagnetic dynamics result in ∼ 4 orders lower energy-per-bit and ∼ 3 orders smaller latency for the SMART memory as compared to prior NVMs such as STT-MRAM and PCM.

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“…Also note that such approaches are conceptionally similar to design obfuscation leveraging traditional field-programmable gate arrays (FPGAs). In [162] and [161,163], polymorphic and obfuscated logic has been studied, based on domain-wall motion devices and on giant spin-Hall effect (GSHE) devices, respectively. One important benefit of the latter studies over the former is that they support all 16 possible functions per device; this renders these devices superior in terms of SAT resilience [161,163].…”

Section: Spintronicsmentioning

confidence: 99%

Hardware Security For and Beyond CMOS Technology

Knechtel¹

2020

Proceedings of the 2020 International Symposium on Physical Design

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As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges. CCS CONCEPTS• Security and privacy → Security in hardware; • Hardware → Emerging technologies.

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Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Cited by 44 publications

References 37 publications

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory

Hardware Security For and Beyond CMOS Technology

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