Advantages and challenges of high performance CMOS on SOI

Pelella, M.M.; Maszara, W.; Sundararajan, S.; Sinha, Soumendu; Wei, A.; Ju, D.-H.; En, W.G.; Krishnan, S.; Chan, Darius K.-S.; Chan, S.S.M.; Yeh, P.; Lee, M.; Wu, Dake; Fuselier, M.; vanBentum, R.; Burbach, G.; Lee, C.; Hill, G.N.; Greenlaw, D.; Riccobenc, C.; Karlsson, Olov; Wristers, D.; Kepler, N.

doi:10.1109/soic.2001.957957

Cited by 10 publications

(5 citation statements)

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“…Then a monolithic integration of the microcantilevers and the CMOS circuitry by using both the silicon-on-insulator (SOI) CMOS and the SOI micromachining technologies is provided. This integration method leads to not only the feasibility of fabrication, but also to circuit improvements in power consumption, the signal-to-noise ratio, signal loss, and so on [19], [20].…”

Section: Introductionmentioning

confidence: 99%

Design of High-Sensitivity Cantilever and Its Monolithic Integration With CMOS Circuits

Tang

Zhang

et al. 2007

IEEE Sensors J.

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Rectangular piezoresistive cantilevers with stress concentration holes opened were designed and fabricated in order to increase the response signals of piezoresistive cantilever first. Both the simulations and the measurements on the cantilever sensitivity show that this design can obviously result in an improvement on the displacement sensitivity of the piezoresistive cantilever. After a characterization study on the piezoresistive cantilever, a monolithic integration of the microcantilever array with a complementary metal-oxide-semiconductor (CMOS) readout circuitry based on the silicon-on-insulator (SOI) CMOS and the SOI micromachining technologies was designed. A cantilever array, a digital controlled multiplexer, and an instrumentation amplifier compose the integrated sensor system, and post-CMOS process was designed to fabricate the integrated system. The measurement results on the SOI CMOS circuitry of the integrated system prove a feasibility of the integration design.

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Section: Introductionmentioning

confidence: 99%

Design of High-Sensitivity Cantilever and Its Monolithic Integration With CMOS Circuits

Tang

Zhang

et al. 2007

IEEE Sensors J.

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“…These problems are further reduced in the new configuration of Double-Gate MOSFET i.e. FinFET [7][8][9].…”

Section: Double-gate Mosfet Device Structurementioning

confidence: 99%

Simulated Analysis of Double-Gate MOSFET and FinFET Structure Using High-k Materials

Srivastava

Bose

2021

Communications in Computer and Information Science

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In this paper, the concept of non-conventional transistors has been presented. Both Double-Gate MOSFET and FinFET have tremendous potential for reducing short-channel effects and high leakage current. With the advancement in the nanometer technology, chip density and operating frequency is increasing leading to the more and more power consumption of battery operated portable devices. Hence, to meet all these challenges including scaling, Double-Gate MOSFET and FinFET are the promising substitutes for the bulk CMOS structures. The devices have been developed and are compared to conventional MOSFET structures which provide wider benefits.

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“…PD device has advantages in most aspects, but kink effects caused by the floating body effect are the key problems. As a solution to the kink effects, body contacts are added to the PD device to eliminate the floating body effect [7,8]. III.…”

Section: B Partly Depleted Soi Smos and Simulationsmentioning

confidence: 99%

Monolithic Integration of Micro-cantilever with Conditioning Circuits based on SOI Techniques

Zhang

Wang

et al. 2006

2006 1st IEEE International Conference on Nano/Micro Engineered and Molecular Systems

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This paper presents a monolithic integration of piezoresistive micro-cantilevers with CMOS (Complementary Metal Oxide Semiconductor) analog amplifier and digital multiplexer based on the techniques of SOI (Silicon On Insulator) CMOS and MEMS (Micro Electronic Mechanical System). The three modules, signal detection, signal selection and signal amplification, of the design are proposed step by step. Then, SOI-CMOS-PD (Partially Depleted) is compared with SOI-CMOS-FD (Fully Depleted) to ensure its advantages in analog IC. And the post-CMOS process is designed as manufacture solution. Finally, simulations and test results are presented to prove the availability of the whole project.

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Advantages and challenges of high performance CMOS on SOI

Cited by 10 publications

References 0 publications

Design of High-Sensitivity Cantilever and Its Monolithic Integration With CMOS Circuits

Design of High-Sensitivity Cantilever and Its Monolithic Integration With CMOS Circuits

Simulated Analysis of Double-Gate MOSFET and FinFET Structure Using High-k Materials

Monolithic Integration of Micro-cantilever with Conditioning Circuits based on SOI Techniques

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