Affinity-On-Next-Touch: An Extension to the Linux Kernel for NUMA Architectures

Lankes, Stefan; Bierbaum, Boris; Bemmerl, Thomas

doi:10.1007/978-3-642-14390-8_60

Cited by 8 publications

(7 citation statements)

References 8 publications

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“…Hardware Performance Monitoring Units (PMU) can be used during application execution [6,21,32] to sample a limited number of events, such as long-latency or DTLB misses. The virtual memory system can be used to lock pages to detect access to them on faults and record the thread and address accessed [7,14,19,21]. This approach does not require sampling, and can collect more detailed information for first/next-touch policies [14,19] but the overhead of locking/unlocking and trapping is greater than querying the PMU.…”

Section: Collecting Memory Informationmentioning

confidence: 99%

“…The virtual memory system can be used to lock pages to detect access to them on faults and record the thread and address accessed [7,14,19,21]. This approach does not require sampling, and can collect more detailed information for first/next-touch policies [14,19] but the overhead of locking/unlocking and trapping is greater than querying the PMU. Binary instrumentation [2,11,33] can also track page accesses by threads and avoid sampling, but the standard tool, Pin [22] incurs a 10-20× [2] overhead.…”

Section: Collecting Memory Informationmentioning

confidence: 99%

See 1 more Smart Citation

Efficient thread/page/parallelism autotuning for NUMA systems

Popov

Jimborean

Black-Schaffer

2019

Proceedings of the ACM International Conference on Supercomputing

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Current multi-socket systems have complex memory hierarchies with significant Non-Uniform Memory Access (NUMA) effects: memory performance depends on the location of the data and the thread. This complexity means that thread-and data-mappings have a significant impact on performance. However, it is hard to find efficient data mappings and thread configurations due to the complex interactions between applications and systems. In this paper we explore the combined search space of thread mappings, data mappings, number of NUMA nodes, and degreeof-parallelism, per application phase, and across multiple systems. We show that there are significant performance benefits from optimizing this wide range of parameters together. However, such an optimization presents two challenges: accurately modeling the performance impact of configurations across applications and systems, and exploring the vast space of configurations. To overcome the modeling challenge, we use native execution of small, representative codelets, which reproduce the system and application interactions. To make the search practical, we build a search space by combining a range of state of the art thread-and data-mapping policies. Combining these two approaches results in a tractable search space that can be quickly and accurately evaluated without sacrificing significant performance. This search finds non-intuitive configurations that perform significantly better than previous works. With this approach we are able to achieve an average speedup of 1.97× on a four node NUMA system.

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Section: Collecting Memory Informationmentioning

confidence: 99%

Section: Collecting Memory Informationmentioning

confidence: 99%

Efficient thread/page/parallelism autotuning for NUMA systems

Popov

Jimborean

Black-Schaffer

2019

Proceedings of the ACM International Conference on Supercomputing

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“…The Solaris operating system offers the next-touch policy [3] that takes a memory page already allocated and migrates it in order to improve its locality with the thread that uses it. Integration of this next-touch policy into the Linux kernel has also been proposed [18,20]. Starting from version 3.8 released in 2013, the Linux kernel also provides NUMA memory balancing [1].…”

Section: Runtime Placementmentioning

confidence: 99%

NumaMMA

Selva

Morel

Marquet

2018

Proceedings of the 47th International Conference on Parallel Processing

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Non Uniform Memory Access (NUMA) architectures are nowadays common for running High-Performance Computing (HPC) applications. In such architectures, several distinct physical memories are assembled to create a single shared memory. Nevertheless, because there are several physical memories, access times to these memories are not uniform depending on the location of the core performing the memory request and on the location of the target memory. Hence, threads and data placement are crucial to efficiently exploit such architectures. To help in taking decision about this placement, profiling tools are needed. In this work, we propose NUMA MeMory Analyzer (NumaMMA), a new profiling tool for understanding the memory access patterns of HPC applications. NumaMMA combines efficient collection of memory traces using hardware mechanisms with original visualization means allowing to see how memory access patterns evolve over time. The information reported by NumaMMA allows to understand the nature of these access patterns inside each object allocated by the application. We show how NumaMMA can help understanding the memory patterns of several HPC applications in order to optimize them and get speedups up to 28% over the standard non optimized version.

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“…Different algorithms have been proposed to spread application data across different memories of an NUMA platform, such as round-robin, first touch affinity and next-touch affinity [32,37]. An extension to Linux kernel to add support for the affinity-on-next-touch algorithm is reported in [38].…”

Section: Related Workmentioning

confidence: 99%

Exploiting architectural features of a computer vision platform towards reducing memory stalls

Mustafa

O’Riordan

Rogers

et al. 2018

J Real-Time Image Proc

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Computer vision applications are becoming more and more popular in embedded systems such as drones, robots, tablets, and mobile devices. These applications are both compute and memory intensive, with memory bound stalls (MBS) making a significant part of their execution time. For maximum reduction in memory stalls, compilers need to consider architectural details of a platform and utilize its hardware components efficiently. In this paper, we propose a compiler optimization for a vision-processing system through classification of memory references to reduce MBS. As the proposed optimization is based on the architectural features of a specific platform, i.e., Myriad 2, it can only be applied to other platforms having similar architectural features. The optimization consists of two steps: affinity analysis and affinity-aware instruction scheduling. We suggest two different approaches for affinity analysis, i.e., source code annotation and automated analysis. We use LLVM compiler infrastructure for implementation of the proposed optimization. Application of annotation-based approach on a memory-intensive program shows a reduction in stall cycles by 67.44%, leading to 25.61% improvement in execution time. We use 11 different image-processing benchmarks for evaluation of automated analysis approach. Experimental results show that classification of memory references reduces stall cycles, on average, by 69.83%. As all benchmarks are both compute and memory intensive, we achieve improvement in execution time by up to 30%, with a modest average of 5.79%.

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Affinity-On-Next-Touch: An Extension to the Linux Kernel for NUMA Architectures

Cited by 8 publications

References 8 publications

Efficient thread/page/parallelism autotuning for NUMA systems

Efficient thread/page/parallelism autotuning for NUMA systems

NumaMMA

Exploiting architectural features of a computer vision platform towards reducing memory stalls

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