Affordable and process window increasing full chip ILT masks

Abstract

To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k 1 lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications [1,2] , it has been shown that the Inverse Synthesizer (IS™) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask.To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

Enhancing fullchip ILT mask synthesis capability for IC manufacturability

“…The mask simplification does not fundamentally change the lower frequency effects determined by main feature and sraf size and placement, as it only perturbs the boundaries of these mask shapes. Thorough studies have been done in collaboration with fracturing companies and mask shops which show that ILT mask write times can approach traditional OPC times and are well within required level needed for production [8] [9].…”

“…Besides the standard MRC rules which must be met, there are numerous other controls which are available to the user. The portion of the mask cost under the user's control is the shot count, and there are numerous tunable controls which make a range of solutions possible [8] [9]. In contrast with standard OPC engines which segment the target design before correcting the mask, ILT allows the segmentation to be done automatically using the raw mask as a guide for segmentation placement and size.…”

Inverse lithography technology: 30 years from concept to practical, full-chip reality

“…52 Jue-Chin Yu from the National Jiaotong University in Taiwan also worked in this area and showed SRAF generation using ILT. 53 By 2010, three companies had demonstrated and published the use of ILT to correct full-chip designs: Luminescent [54][55][56][57][58] (later acquired by Synopsys, Inc.), which employed the level-set method of ILT optimization, Intel 30 using pixelated PSM mask, and Gauda 33 (later acquired by D2S, Inc.), which presented a GPU-accelerated approach using a cost-function in the frequency domain. Other semiconductor manufacturing companies produced full-chip correction using ILT but never published their results.…”

“…In the early days of ILT, many techniques were explored, mainly by Luminescent and its partners, to reduce the shot count while minimizing the loss of process window. 55,56 As we have discussed, the standard approach to adapting curvilinear ILT patterns to VSB mask writers is to Manhattanize, or fracture, the curved design into small rectilinear shapes that are grouped to approximate the curvilinear contours. As shown in Fig.…”

Computational lithography: Exhausting the resolution limits of 193-nm projection lithography systems

“…In practice it then becomes possible to stitch together relatively small regions of the mask layout that have been optimized in parallel independently. 136,[138][139][140] Customized hardware platform acceleration has also been explored as a means to address the computational burden of full-chip optimization, with attempts with graphics processing unit based solutions. Specialized techniques have been developed to accomplish mask optimization with a fixed source, including methods to calculate function gradients using fast Fourier transforms.…”