Aggressive EOT Scaling of Ge pMOSFETs With HfO2/AlO&lt;italic&gt;x&lt;/italic&gt;/GeO&lt;italic&gt;x&lt;/italic&gt;Gate-Stacks Fabricated by Ozone Postoxidation

Zhang, Rui; Tang, Xiaoyu; Yu, Xiao; Li, Junkang; Zhao, Yi

doi:10.1109/led.2016.2572731

Cited by 53 publications

(20 citation statements)

References 20 publications

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“…Ge pMOSFETs with these S/D junctions were also achieved by gate-first process. Following pre-cleaning of Ge wafer and definition of active area, the Al 2 O 3 (5 nm)/GeO x (∼1 nm) gate stack was deposited by atomic layer deposition (ALD) and in-situ ozone post oxidation (OPO) at 300 • C [2]. The metallic NiGe S/D were formed by the same annealing conditions mentioned above.…”

Section: A Junction and Device Fabricationmentioning

confidence: 99%

“…Figure 12(b) shows that trapping free characteristics are obtained when measuring from DC to 1 µs. On one hand, the difference with SS behaviors at different measurement speeds is neglectable due to the well-passivated MOS interface by OPO [2]. On the other hand, the TAT currents are significantly suppressed with the suppression of junction traps under the fast I-V measurement, resulting in the decreased OFF-state currents.…”

Section: B Demonstration Of the Validity For D T Extractionmentioning

confidence: 99%

“…Ge has been attracting a lot of interests as the channel material for future CMOS technology, owing to its high bulk mobility [1]. Much attentions have been focused on the research of the Ge MOS interface and its impact on device performance [2]- [6]. However, the problem for Ge junctions is still lack of mechanism study.…”

Section: Introductionmentioning

confidence: 99%

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Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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This paper proposes and develops a new technique based on low temperature conductance method to quantitatively evaluate the trap densities around NiGe/Ge Schottky junction interface and their time constants. It is found that the Schottky barrier height (SBH) in the NiGe/Ge junction is related with these junction traps. Additionally, the traps around junction interface could strongly affect the electrical properties of Ge MOSFETs, especially the OFF-state currents. INDEX TERMS Germanium, Schottky junction, traps around junction interface, low temperature conductance method.

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Section: A Junction and Device Fabricationmentioning

confidence: 99%

Section: B Demonstration Of the Validity For D T Extractionmentioning

confidence: 99%

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Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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“…为了进一步优化 SiGe n-FinFET 的电学特性, IBM 在 2018 年通过在应力释放缓冲层 (strain relaxed buffer, SRB) 上外延不同组分的 SiGe 层得到了具有拉应力的沟道 [83] . 由于拉应力的引入, 造成了沟道载流子的有效质量降低, 从而提升了晶体管的迁移率和电流特性, 在 Ge 组分为 10% 时, 拉 Si [14] Si [12] Si [13] SiGe [14] SiGe [15] Ge [16] Ge [6] sGe Fin [18] This work ( 新沟道材料 Ge 也是近年来研究的热门. 2012 年, 台积电 (TSMC) 利用 ART 技术首次展示了 Ge 基 p-FinFET [84] .…”

Section: Sige/ge 基鳍式场效应晶体管unclassified

Research progress in Ge-based advanced field effect transistor technology

Zhao¹,

Zheng²,

Li³

2020

Sci. Sin.-Inf.

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摘要传统硅 (Si) 基集成电路制造工艺已经进入 7 nm 节点, 继续减小器件尺寸变得愈发困难. 半导体材料锗 (Ge), 具有比硅更高的载流子迁移率, 能够实现器件性能的大幅提升. 本文从栅极堆垛 (gate stack)、源漏工程 (source/drain engineering) 和新器件结构 (new device structures) 3 个角度总结了 Ge 器件的最新研究成果. 研究表明, 锗沟道器件中诸多关键科学和工程问题仍未得到有效解决, 从基本的器件制备工艺到深层次的器件物理问题都亟待深入研究与克服. 但是, Ge 器件是未来集成电路 5 nm 及以下技术节点最有希望的发展方向. 关键词锗, 栅极堆垛, 源漏技术, 新器件结构 1 引言金属-氧化物-半导体场效应晶体管 (metal-oxide-semiconductor field effect transistor, MOSFET) 是现代集成电路的基础. 目前量产级的 Si MOSFET 技术节点已经达到 7 nm, 进一步缩短沟道长度将导致器件出现一系列负面现象 (短沟道效应、功耗升高等) (图 1(a)) [1∼3]. 尽管 Intel 公司开发了鳍式晶体管 (FinFET), 增强了器件栅极的静电控制能力, 一定程度上抑制了短沟道效应 (图 1(b)) [4] , 但是随着技术节点的不断推进, 上述问题还是越来越严重, 器件性能提升面临着严峻的挑战. 为了提升器件的电学性能, 产业界和学术界从新材料和新结构两方面提出了可能的解决方案. 从引入新沟道材料角度看, 采用更高载流子迁移率的半导体材料作为器件沟道, 能够在不改变器件结构和尺寸的情况下获得更大的驱动电流 I D , 这一技术路线已经在 90 nm 技术节点中得到了验证 [5]. 国际上各大半导体厂商 (Intel, IBM, TSMC 等) 和诸多科研机构 (斯坦福大学 (Stanford University)、麻

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“…The impact of temperature on GeO x thickness grown by ozone on Ge surface was demonstrated. Ge pMOSFETs with GeO x passivation fabricated by ozone post oxidation was also reported [9].…”

Section: Introductionmentioning

confidence: 99%

Ge pMOSFETs with GeOx Passivation Formed by Ozone and Plasma Post Oxidation

Han

Liu

et al. 2019

Nanoscale Res Lett

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A comparison study on electrical performance of Ge pMOSFETs with a GeO x passivation layer formed by ozone post oxidation (OPO) and plasma post oxidation (PPO) is performed. PPO and OPO were carried out on an Al 2 O 3 /n-Ge (001) substrate followed by a 5-nm HfO 2 gate dielectric in situ deposited in an ALD chamber. The quality of the dielectric/Ge interface layer was characterized by X-ray photoelectron spectroscopy and transmission electron microscopy. The PPO treatment leads to a positive threshold voltage ( V TH ) shift and a lower I ON / I OFF ratio, implying a poor interface quality. Ge pMOSFETs with OPO exhibit a higher I ON / I OFF ratio (up to four orders of magnitude), improved subthreshold swing, and enhanced carrier mobility characteristics as compared with PPO devices. A thicker Al 2 O 3 block layer in the OPO process leads to a higher mobility in Ge transistors. By comparing two different oxidation methods, the results show that the OPO is an effective way to increase the interface layer quality which is contributing to the improved effective mobility of Ge pMOSFETs.

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Aggressive EOT Scaling of Ge pMOSFETs With HfO₂/AlO_{<italic>x</italic>}/GeO_{<italic>x</italic>}Gate-Stacks Fabricated by Ozone Postoxidation

Cited by 53 publications

References 20 publications

Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices

Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices

Research progress in Ge-based advanced field effect transistor technology

Ge pMOSFETs with GeOx Passivation Formed by Ozone and Plasma Post Oxidation

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