Aggressive Exclusion of Scan Flip-Flops from Compression Architecture for Better Coverage and Reduced TDV: A Hybrid Approach

Shantagiri, Pralhadrao V.; Kapur, R.

doi:10.3390/jlpea9020018

Cited by 3 publications

(4 citation statements)

References 36 publications

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“…According to [10], the suggested AE approach greatly boosts fault identification and enhances TC. To increase product production and lower DPM, the TC plays a crucial role.…”

Section: Literature Reviewmentioning

confidence: 99%

A Novel Techniques to Reduce the Test Data Volume and Test Time for General Configurations by Embedded Deterministic Testing

swamy G M

2023

Preprint

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<p>The main goal of Design for Testability (DFT) is to offer a way to test each node in the design (Netlist) for different kinds of defects in the chip. These nodes that are to be checked by using the intended number of patterns, the more thoroughly the design has been tested. Every node in the architecture must be visible(observable) and controlled for this to be achievable. These two concepts may be thought of as the cornerstones of DFT, which must be adhered to in order to get the most test coverage with the fewest possible patterns. This work is applied in the field of IC manufacturing before IC gets fabricated. The parameters like multi-voltages and temperature of IC will be determined with the help of Scan Insertion, ATPG pattern generation, EDT test compression and simulation using mentor graphics tool. In this script we are mainly concentrated on the compression process of the data volume and test time by generating automatic test patterns according to it and simulating </p>

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“…According to [10], the suggested AE approach greatly boosts fault identification and enhances TC. To increase product production and lower DPM, the TC plays a crucial role.…”

Section: Literature Reviewmentioning

confidence: 99%

A Novel Techniques to Reduce the Test Data Volume and Test Time for General Configurations by Embedded Deterministic Testing

swamy G M

2023

Preprint

View full text Add to dashboard Cite

show abstract

“…According to [10], the suggested AE approach greatly boosts fault identification and enhances TC. To increase product production and lower DPM, the TC plays a crucial role.…”

Section: Literature Reviewmentioning

confidence: 99%

A Novel Techniques to Reduce the Test Data Volume and Test Time for General Configurations by Embedded Deterministic Testing

swamy G M

2023

Preprint

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“…The various code-based schemes are proposed in [5][6][7][8]. The code-based test compression methods are usually inefficient in TAT reduction [25] and require complex control logic [9].…”

Section: Code-based Scan Compression Architecturementioning

confidence: 99%

“…It showed TDV could be improved by excluding SFFs capturing Xs from the compression architecture and placing them in an external scan chain. In [25], profiling of SFFs and excluding them from the compression architecture is studied and the study was limited to the last 95% of the patterns generated and created a higher number of the external scan chains to improve the TDV. In [26], a reconfigurable broadcasting technique using Internal Joint Task Action Group (IJTAG) to test identical cores is proposed.…”

Section: Broadcast-based Scan Compression Architecturementioning

confidence: 99%

New scan compression approach to reduce the test data volume

Shantagiri

Kapur

Shastry

2021

IET Computers & Digital Tech

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The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip‐flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic‐0 and logic‐1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.

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Aggressive Exclusion of Scan Flip-Flops from Compression Architecture for Better Coverage and Reduced TDV: A Hybrid Approach

Cited by 3 publications

References 36 publications

A Novel Techniques to Reduce the Test Data Volume and Test Time for General Configurations by Embedded Deterministic Testing

A Novel Techniques to Reduce the Test Data Volume and Test Time for General Configurations by Embedded Deterministic Testing

A Novel Techniques to Reduce the Test Data Volume and Test Time for General Configurations by Embedded Deterministic Testing

New scan compression approach to reduce the test data volume

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