Aggressive inlining

Ayers, Andrew; Schooler, Richard; Gottlieb, Robert

doi:10.1145/258916.258928

Cited by 20 publications

(13 citation statements)

References 11 publications

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“…Ayers et al [20] describe an aggressive inliner, based on profile information, which is able to inline procedures without restriction at almost any call site. Their results show that aggressive inlining can provide important performance improvements in some benchmarks.…”

Section: Code Optimizationmentioning

confidence: 99%

Enlarging Instruction Streams

Desmet

Verbaeten

Joosen

et al. 2007

IEEE Trans. Comput.

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Abstract-The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially containing multiple basic blocks, a stream. The long length of instruction streams makes it possible for the stream fetch engine to provide a high fetch bandwidth and to hide the branch predictor access latency, leading to performance results close to a trace cache at a lower implementation cost and complexity. Therefore, enlarging instruction streams is an excellent way to improve the stream fetch engine. In this paper, we present several hardware and software mechanisms focused on enlarging those streams that finalize at particular branch types. However, our results point out that focusing on particular branch types is not a good strategy due to Amdahl's law. Consequently, we propose the multiple-stream predictor, a novel mechanism that deals with all branch types by combining single streams into long virtual streams. This proposal tolerates the prediction table access latency without requiring the complexity caused by additional hardware mechanisms like prediction overriding. Moreover, it provides high-performance results which are comparable to state-of-the-art fetch architectures but with a simpler design that consumes less energy.

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Section: Code Optimizationmentioning

confidence: 99%

Enlarging Instruction Streams

Desmet

Verbaeten

Joosen

et al. 2007

IEEE Trans. Comput.

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“…The other primary assumption in the CRISP work is that function calls are frequent and that overhead of the function linkage mechanism is very important to overall performance. This is still true today ( [74,75]) so an important criterion of a register-architecture is how it handles function calls.…”

Section: No Architected Register Filementioning

confidence: 99%

Smart Register Files for High-Performance Microprocessors

Postiff

Mudge²

1999

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This report examines how the compiler can more efficiently use a large number of processor registers. The placement of data items into registers, called register allocation, is known to be one of the most important compiler optimizations for high-speed computers because registers are the fastest storage devices in the computer system. However, register allocation has been limited in scope because of aliasing in the memory system. To break this limitation and allow more data to be placed into registers, new compiler and microarchitecture support is needed.We propose the modification of register access semantics to include an indirect access mode. We call this optimization the Smart Register File. The smart register file allows the relaxation of overly-conservative assumptions in the compiler by having the hardware provide support for aliased data items in processor registers. As a result, the compiler can allocate data from a larger pool of candidates than in a conventional system. An attendant advantage is that the smart register file reduces the number of load and store operations executed by the processor. The simple addition of an indirect register access mode not only simplifies alias handling, but also provides opportunities for other optimizations. This dissertation examines several such optimizations. Report Documentation PageForm Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number.

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“…• HLO: This setup uses the previous interprocedural optimizer in the HP-UX compilers based on the framework presented in [2,3]. The set of optimizations performed in this setup is equivalent to the SYZYGY setup.…”

Section: Resultsmentioning

confidence: 99%

“…A traditional approach such as [2] works on the raw program representation during the inlining phase. While this works pretty well for small programs, the memory consumption of the compiler easily hits the system limit for larger applications.…”

Section: Cross-module Procedures Inliningmentioning

confidence: 99%

“…The approach presented in [2] performs several iterations of procedure inlining and scalar optimizations in order to accurately capture the impact of post-inline optimizations to assist subsequent inlining decision. While this works pretty well for achieving run-time performance, it is usually disastrous for compilation time while compiling large applications.…”

Section: Cross-module Procedures Inliningmentioning

confidence: 99%

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