Aging comparative analysis of high-performance FinFET and CMOS flip-flops

Taghipour, Shiva; Asli, Rahebeh Niaraki

doi:10.1016/j.microrel.2016.12.012

Cited by 25 publications

(4 citation statements)

References 13 publications

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“…Together, these lead to increased onchip temperatures which potentially accelerate the wearout effects. 52,53 Besides, the thermal resistance (R th ) of the multi-gate topology and the reduced gate pitch in Fin-FET devices exacerbate self-heating which will accelerate aging. 54 Figure 16 shows our simulation results with the industrial aging models; the results show a very significant performance degradation under accelerated stress condition, and if we scale this to the normal operating condition (nominal V dd and normal on-chip temperature), the degradation is still much larger than that in the planar devices.…”

Section: Variability and Reliabilitymentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Section: Variability and Reliabilitymentioning

confidence: 99%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

View full text Add to dashboard Cite

show abstract

“…Considering these problems, the primary challenge for the design engineers is inadequate, realization within a targeted power without compromising the performance requirement. [1][2][3][4][5][6][7][8][9][10][11][12][13] The tiny size of the MOSFET, less than tens of nanometers, created some operational problems such as high sub-threshold conduction which means; in the MOSFET, the applied voltage to gate terminal is to be decreased to maintain the reliability. [2][3] Then the threshold voltage which is to be applied to the MOSFET must also be reduced.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Dependent Arithmetic Module Realization for High-Speed Computing

2023

VLSI

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Since last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

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“…So it leads only to parametric time-dependent variability, affecting mainly delay and leakage power. If the neurons and synapses in a neuromorphic hardware are used continuously for long duration at elevated operating conditions, the parameter drifts cannot be reversed [100], leading to permanent functional degradation of the circuit and eventually, hardware faults [53,68,91]. The permanent fault rates in integrated circuits can be described by the bathtub curve as shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Reliability Management in Neuromorphic Computing

Song

Hanamshet

Balaji

et al. 2021

J. Emerg. Technol. Comput. Syst.

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Neuromorphic computing systems execute machine learning tasks designed with spiking neural networks. These systems are embracing non-volatile memory to implement high-density and low-energy synaptic storage. Elevated voltages and currents needed to operate non-volatile memories cause aging of CMOS-based transistors in each neuron and synapse circuit in the hardware, drifting the transistor’s parameters from their nominal values. If these circuits are used continuously for too long, the parameter drifts cannot be reversed, resulting in permanent degradation of circuit performance over time, eventually leading to hardware faults. Aggressive device scaling increases power density and temperature, which further accelerates the aging, challenging the reliable operation of neuromorphic systems. Existing reliability-oriented techniques periodically de-stress all neuron and synapse circuits in the hardware at fixed intervals, assuming worst-case operating conditions, without actually tracking their aging at run-time. To de-stress these circuits, normal operation must be interrupted, which introduces latency in spike generation and propagation, impacting the inter-spike interval and hence, performance (e.g., accuracy). We observe that in contrast to long-term aging, which permanently damages the hardware, short-term aging in scaled CMOS transistors is mostly due to bias temperature instability. The latter is heavily workload-dependent and, more importantly, partially reversible. We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems by designing an intelligent run-time manager (NCRTM), which dynamically de-stresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target. NCRTM de-stresses these circuits only when it is absolutely necessary to do so, otherwise reducing the performance impact by scheduling de-stress operations off the critical path. We evaluate NCRTM with state-of-the-art machine learning workloads on a neuromorphic hardware. Our results demonstrate that NCRTM significantly improves the reliability of neuromorphic hardware, with marginal impact on performance.

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Aging comparative analysis of high-performance FinFET and CMOS flip-flops

Cited by 25 publications

References 13 publications

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era

Machine Learning Dependent Arithmetic Module Realization for High-Speed Computing

Dynamic Reliability Management in Neuromorphic Computing

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