Aging Mechanism of p-Type Dopingless JLFET: NBTI and Channel-Hot-Carrier Stress

Panchore, Meena; Rajan, Chithraja

doi:10.1007/s42341-022-00428-2

Cited by 6 publications

(9 citation statements)

References 17 publications

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“…The device structures are illustrated in Figure 1A–D for n‐ and p‐type HKV‐DGJLFETs, and HKV‐DGDLJLFETs. The device parameters of structures are taken uniform excluding gate work function and doping concentration 5 . The doping concentration of silicon (Si) body of n‐type HKV‐DGJLFET is taken very high which is of

{10}^{19}{\mathrm{cm}}^{\hbox{-} 3}

and the metal gate work function

\left({\phi}_g\right)

is considered 5.5 eV.…”

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

“…To induce negative charges in the S/D region of HKV‐DGDLJLFET, the gate metal work function has been used 3.9 eV (hafnium). The essential requirements of the CP concept are explained in detail in Reference 5. The parameters of vacuum based structures are listed in Table 1.…”

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

“…In DLJLFET structure, the silicon region doping is almost intrinsic; therefore, it is less susceptible to RDF and exhibits higher ON‐state current and smaller leakage current. Also, the electric filed in dopingless structure is quite less than conventional junctionless structure, thus making it more reliable from aging effect due to CHC 5–9 . However, the reliability of these scaled‐up devices has become extremely important and it depends on other stress factors also, for example, bias temperature instability (BTI).…”

Section: Introductionmentioning

confidence: 99%

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Assessment of BTI‐induced deterioration in vacuum based undoped structure

Kumar,

Panchore

2024

Int J Numerical Modelling

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In this paper, an assessment of bias temperature instability (BTI) in based dual gate dopingless JLFET (HKV‐DLJLFET) is carried out at 15 nm technology node. For this, the gate dielectric of HKV‐DGDLJLFET is made of asymmetric combination of and vacuum dielectrics near the source/drain (S/D) side, which significantly minimizes the leakage current and enhances the reliability. Our simulation study have shown that the n‐type HKV‐DGDLJLFET exhibits 2.28 and 2.45 times less deterioration in drain current and transconductance respectively, than n‐type HKV‐DGJLFET due to positive BTI (PBTI) for 2000 seconds at . Further, we have found that n‐type HKV‐DGDLJLFET has less deterioration in and due to BTI stress for different time spans. Hence, adding vacuum dielectric to the drain side lowers the BTI stress at high temperatures and makes it last longer.

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{10}^{19}{\mathrm{cm}}^{\hbox{-} 3}

and the metal gate work function

\left({\phi}_g\right)

is considered 5.5 eV.…”

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

Section: Simulation Parameters and Device Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Kumar,

Panchore

2024

Int J Numerical Modelling

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“…The immunity of GSI-NWM against aging and hot carrier effects is a crucial factor that needs to be addressed because the reliability of the proposed structure can be affected by various factors that can cause degradation in their performance [60][61][62]. Aging effects result in performance degradation and, eventually, failure of circuits.…”

Section: Effect Of Doping On Analog Performance Evaluation Characteri...mentioning

confidence: 99%

Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET

et al. 2023

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This paper critically investigates the effect of doping on different device characteristics of a Ge/Si interfaced nanowire MOSFET (GSI-NWM) for analog performance enhancement. The doping of source, channel, and drain has a prominent effect on important device characteristics, which has been investigated through DC and AC analysis performed on the SILVACO TCAD simulator. A numerical computational-based simulation study has been used to investigate the modulation of various device characteristics, such as threshold voltage, cut-off frequency, subthreshold swing, MTPG, current ratio, channel resistance, and transconductance. The investigation revealed a strong dependence of most of these characteristics on the source, channel, and drain doping levels, providing valuable insights into device performance. Proper optimization in doping can significantly improve the performance of the device. A compact physics-based analytical model has been mathematically evaluated and proposed in this work, showing an excellent in-line agreement with the simulated results. This is a novel approach for improving the analog performance parameters of a nanowire MOSFET through doping optimization, which incorporates gate oxide stacking and germanium as a source material. In this work, the biosensing capability of the GSI-NWM has also been discussed and evaluated.

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“…Das et al [19] have investigated the effect of doping on the performance of Ge/Si interfaced nanowire MOSFET. Further, Panchore et al [20] have analysed the aging mechanism of p-type dopingless Junctionless field effect transistor for the first time. The channel hot carrier conditions and negative bias temperature instability effects are considered.…”

Section: Introductionmentioning

confidence: 99%

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

Mehta,

Kumar Arya,

Sharma

2024

Eng. Res. Express

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The detailed performance analysis of Core Shell Gate All Around junctionless field effect transistor along with CMOS inverter as an application with quantum models is presented in this paper for the first time. To appreciate the performance of the device and the application even at smaller channel length, the comparison with classical models is also presented. The OFF current was calculated as 3.6810-16A on incorporating the quantum models. The subthreshold swing (SS) and Drain induced barrier lowering (DIBL) are found to be near ideal values. The SS and DIBL was calculated as 62.82mV/dec and 33.4mV/V. The DIBL was found to be lesser by 52.82% with quantum model than classical model. The performance obtained using quantum models are better than the classical models in terms of different parameters such as OFF current, ON current, SS, DIBL, threshold voltage, transconductance. Further, the performance of the CMOS inverter with quantum models by considering the n-type and p-type Core Shell Gate All Around junctionless field effect transistor is also presented . The OFF current of p-type and n-type was matched before designing the application. A sharp transfer characteristics of the CMOS inverter is obtained. The performance was also studied by calculating the drain current from each of p-type and n-type and found to be more than 110-7A and SNM (Static Noise Margin) was calculated as 267mV. The transient response of CMOS inverter exhibits the potential of CMOS inverter using the proposed device even at smaller channel lengths.

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Aging Mechanism of p-Type Dopingless JLFET: NBTI and Channel-Hot-Carrier Stress

Cited by 6 publications

References 17 publications

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Assessment of BTI‐induced deterioration in vacuum based undoped structure

Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

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