AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs

Abstract

We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to take advantage of optimisations available in the software compiler flow, and also to provide freedom to the low-level synthesiser, to explore options for application-specific implementations. Two operations become possible -reuse of computational resources across different modules in the design, and generation of an application-specific memory subsystem for faster data accesses.AHIR presents a decoupled view of the program, in terms of control flow, data flow and memory accesses. Each module in AHIR is a triplet consisting of a control-path, datapath and a symbolic association between the two. Memory is represented only by load-store operators, while the memory subsystem is separately designed by the implementor.In the program-to-hardware flow, a module in AHIR corresponds to a function in C. A complete program is a callgraph of functions, which is translated to a set of modules. The call-graph is restricted to be a DAG; recursion is not allowed. The representation is generated by a back-end in the software compiler, which runs after all source-level optimisations have been performed by relevant passes.

A Compiler Infrastructure for Accelerator Generators

“…The input and output ports form the interface to the component and define their size in bits. For example, a component defining a 32-bit integer adder uses these ports: component adder(lhs: 32, rhs: 32) -> (sum: 32) Ports in Calyx are untyped-they can hold any value of a given width. Calyx leaves type-based reasoning to the language frontend.…”

“…Another category of HLS IRs uses finite state machines (FSMs) to model programs' execution schedules at the cycle level [9,32,37]. While such FSM representations are reminiscent of Calyx's control language, these IRs impose restrictions on the timing behavior of the operations inside the FSMs.…”