ALD tungsten NEMS switches and tunneling devices

Davidson, B.; Seghete, Dragos; George, Steven M.; Bright, Victor M.

doi:10.1016/j.sna.2009.07.022

Cited by 27 publications

(22 citation statements)

References 16 publications

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“…Mod kegagalan lesu dan patah (Rajah 7(c)) pula secara umumnya kurang berlaku dalam peranti berskala mikro dan nano tetapi kegagalan ini juga telah diperhatikan dalam kajian lepas (Davidson et al 2011). Sebagai contoh, suis silikon karbida berjulur NEM telah mengalami kegagalan akibat patah atau gabungan patah dan lebur apabila beroperasi pada suhu yang tinggi serta selepas satu bilion kitaran operasi manakala struktur silikon tergantung juga RAJAH 7.…”

Section: Kemajuan Kini Dan Kebolehharapan Peranti Suis Nemunclassified

Peranti Suis Sistem Nanoelektromekanikal (NEMS) Berunsurkan Grafin dan Tiub Nano Karbon (CNT)

Zulkefli

Mohamed

Siow

et al. 2018

JSM

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Pembangunan teknologi nano membuatkan kami meneliti semula satu idea pengkomputeran mekanikal yang dicadangkan oleh Charles Babbage kira-kira dua abad yang lalu. Walaupun idea pengkomputeran mekanikal masih tidak dapat dilaksanakan secara sepenuhnya buat ketika ini kerana isu kebolehharapan yang rendah, tetapi idea ini mempunyai potensi untuk mengatasi kemajuan dalam mikro/ nanoelektronik yang selama ini diwakili oleh hukum Moore yang dicadangkan oleh Gordon Moore pada tahun 1965. Hukum Moore meramalkan bahawa dengan mengurangkan saiz komponen dalam litar berintegrasi, bilangan komponen pada litar berintegrasi ini akan meningkat dua kali ganda setiap dua belas bulan (Moore 1965). Seperkara lagi, apabila kita telah mencapai had penskalaan transistor semikonduktor, had penskalaan ini menandakan masa untuk mencipta dan mereka bentuk transistor semikonduktor yang baru (Theis & Solomon 2012).Kejayaan industri semikonduktor boleh dinilai berdasarkan dua faktor iaitu prestasi ketahanan mekanikal dan proses fabrikasi berskala. Oleh kerana saiz peranti semikonduktor dikurangkan kepada beberapa puluhan nanometer dan permintaan untuk lebih banyak aplikasi terus meningkat, strategi lain amat diperlukan. Sebagai contoh,

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Section: Kemajuan Kini Dan Kebolehharapan Peranti Suis Nemunclassified

Peranti Suis Sistem Nanoelektromekanikal (NEMS) Berunsurkan Grafin dan Tiub Nano Karbon (CNT)

Zulkefli

Mohamed

Siow

et al. 2018

JSM

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“…However, for the critical dimension lower than tens of nanometer, it is reported that the resistivity of Cu is increased sharply due to the size effect related to the long electron mean free path (EMFP) of 39 nm in addition to the decreased reliability of Cu as the device operating temperatures and current densities are increased . As one of possible replacements of Cu, W, which is widely used as an interconnect layer, a diffusion barrier of semiconductor integrated circuits, a gate material for 3D NAND flash memory, etc is investigated for the next generation interconnection material because of the smaller EMFP of 19 nm and a high melting point (3,695 K compared with Cu of 1,357 K) . Since W has a smaller EMFP than Cu, it is expected to reduce the size effect of surface scattering and grain boundary scattering as it goes to nanometer dimension …”

Section: Introductionmentioning

confidence: 99%

Anisotropic atomic layer etching of W using fluorine radicals/oxygen ion beam

Kim

Lee

et al. 2019

Plasma Processes & Polymers

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Atomic layer etching (ALE) has advantages such as precise thickness control, high etch selectivity, and no‐increase in surface roughness which can be applied to sub 10 nm semiconductor device fabrication. In this study, anisotropic ALE of tungsten (W), which is used as an interconnect layer and gate material of semiconductor devices, was investigated by sequentially exposing to F radicals by NF3 plasma to form a WFy layer and following exposure to an oxygen ion beam to remove the WFy layer by forming volatile WOxFy at room temperature. A wide ALE window of F radical adsorption time of ( ≥ 10 s/cycle) and Ox+ ion desorption time of (10 ≤ t ≤ 50 s/cycle at + 44–51 eV of Ox+ ion energy) could be identified, and at the ALE conditions, a precise etch rate of ~2.6 Å/cycle was obtained while increasing the W etch depth linearly with increasing the number of etch cycles. At the optimized W ALE conditions, the W surface roughness after the W ALE was similar to the as‐received W and the etch selectivity over SiO2 was close to infinite. However, after the W ALE, ~ 10% F diffused into W was observed on the etched W surface, and which could be removed by a following process.

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“…8 Since then, ALD films have been demonstrated, e.g., as dielectric layers in RF-MEMS, 9 lubricating films, 10 insulator in MEMS compass, 11,12 mirrors in Fabry-Perot interferometers for visible light, 13,14 antistiction layers, 15 and nanoelectromechanical system switches. 16 The performance and reliability of MEMS devices can be dominated by interfacial phenomena such as adhesion, friction, and wear. 7 Adhesion failure is often the primary failure mechanism of the coating, limiting its applicability and lifetime.…”

Section: Introductionmentioning

confidence: 99%

Microscratch testing method for systematic evaluation of the adhesion of atomic layer deposited thin films on silicon

Kilpi

Ylivaara

Vaajoki

et al. 2015

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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The scratch test method is widely used for adhesion evaluation of thin films and coatings. Usual critical load criteria designed for scratch testing of coatings were not applicable to thin atomic layer deposition (ALD) films on silicon wafers. Thus, the bases for critical load evaluation were established and the critical loads suitable for ALD coating adhesion evaluation on silicon wafers were determined in this paper as LCSi1, LCSi2, LCALD1, and LCALD2, representing the failure points of the silicon substrate and the coating delamination points of the ALD coating. The adhesion performance of the ALD Al2O3, TiO2, TiN, and TaCN+Ru coatings with a thickness range between 20 and 600 nm and deposition temperature between 30 and 410 °C on silicon wafers was investigated. In addition, the impact of the annealing process after deposition on adhesion was evaluated for selected cases. The tests carried out using scratch and Scotch tape test showed that the coating deposition and annealing temperature, thickness of the coating, and surface pretreatments of the Si wafer had an impact on the adhesion performance of the ALD coatings on the silicon wafer. There was also an improved load carrying capacity due to Al2O3, the magnitude of which depended on the coating thickness and the deposition temperature. The tape tests were carried out for selected coatings as a comparison. The results show that the scratch test is a useful and applicable tool for adhesion evaluation of ALD coatings, even when carried out for thin (20 nm thick) coatings.

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ALD tungsten NEMS switches and tunneling devices

Cited by 27 publications

References 16 publications

Peranti Suis Sistem Nanoelektromekanikal (NEMS) Berunsurkan Grafin dan Tiub Nano Karbon (CNT)

Peranti Suis Sistem Nanoelektromekanikal (NEMS) Berunsurkan Grafin dan Tiub Nano Karbon (CNT)

Anisotropic atomic layer etching of W using fluorine radicals/oxygen ion beam

Microscratch testing method for systematic evaluation of the adhesion of atomic layer deposited thin films on silicon

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