Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC

Abstract

High Definition (HD) video compression enables vivid reproduction of scenes. However, Motion Estimation (ME) requires large memory capacity and huge memory bandwidth, which are undesirable in many platforms including ASIC and SoC. In this paper, an algorithm and architecture design of cache system and fast ME in HD H.264/AVC are proposed. With the proposed cache system and hardware-oriented fast ME algorithm, the rate-distortion performance is maintained within 0.03dB difference, the size of on-chip memory reduced to only 10% to 21% of original size, while the external memory bandwidth from cache refill is also 18% to 56% less than that of level C data reuse scheme with vertical 64 search range.

Memory bandwidth-scalable motion estimation for mobile video coding

“…Several approaches have tried to reduce the required data BW. Designs in [18,19] use a cache to maximize the possible data reuse for irregular search patterns. Bus BW-effective ME designs in [20,21] lower the BW requirement by reducing the pixel representation from 8 bits to a binary pattern.…”