Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications

Hsieh, Jui-Hung; Shih, Meng-Ju; Huang, Xingguo

doi:10.1109/tbcas.2018.2871184

Cited by 12 publications

(8 citation statements)

References 28 publications

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“…The proposed concept achieved the high throughput at eight gigabytes per sec with 40% IC ratio and its throughput is superior to prior methods. The study by Hsieh et al [29] presented a VLSI hardware based architecture design with low power, small size and high-performance algorithm design named as SPIHT. The proposed design includes very less code processing time and maintains the high quality while implementing the DWT based ECG image compression data.…”

Section: Related Workmentioning

confidence: 99%

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Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

2020

IJITEE

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The domain of image signal processing, image compression is the significant technique, which is mainly invented to reduce the redundancy of image data in order to able to transmit the image pixels with high quality resolution. The standard image compression techniques like losseless and lossy compression technique generates high compression ratio image with efficient storage and transmission requirement respectively. There are many image compression technique are available for example JPEG, DWT and DCT based compression algorithms which provides effective results in terms of high compression ratio with clear quality image transformation. But they have more computational complexities in terms of processing, encoding, energy consumption and hardware design. Thus, bringing out these challenges, the proposed paper considers the most prominent research papers and discuses FPGA architecture design and future scope in the state of art of image compression technique. The primary aim to investigate the research challenges toward VLSI designing and image compression. The core section of the proposed study includes three folds viz standard architecture designs, related work and open research challenges in the domain of image compression.

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Section: Related Workmentioning

confidence: 99%

“…Achieved 40% IC ratio Not benchmarking Jui et.al [29] To introduce a VLSI hardware based architecture design…”

Section: Haffman Codingmentioning

confidence: 99%

Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

2020

IJITEE

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“…Current literature uses two-band WFBs to analyze ECG signals [4][5][6][7][8][9][10]. Poor resolution (∆ω = π/2) of low and highfrequency bands during signal decomposition is the major drawback of two-band WFBs.…”

Section: Selection Of Wavelet Transform and Filter Bank Architecturementioning

confidence: 99%

Time–frequency localization using three-tap biorthogonal wavelet filter bank for electrocardiogram compressions

2019

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A joint time-frequency localized three-band biorthogonal wavelet filter bank to compress Electrocardiogram signals is proposed in this work. Further, the use of adaptive thresholding and modified run-length encoding resulted in maximum data volume reduction while guaranteeing reconstructing quality. Using signal-to-noise ratio, compression ratio (C R), maximum absolute error (E MA), quality score (Q s), root mean square error, compression time (C T) and percentage root mean square difference the validity of the proposed approach is studied. The experimental results deduced that the performance of the proposed approach is better when compared to the two-band wavelet filter bank. The proposed compression method enables loss-less data transmission of medical signals to remote locations for therapeutic usage.

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“…A VLSI architecture with tree-based approach for towards image encoder based compression is given in Hsieh et al [20]. An energy efficient implementation of VLSI architecture for image compression is introduced in Chen et al [21] considering ultra-high definition frame.…”

Section: Introductionmentioning

confidence: 99%

Novel hybrid framework for image compression for supportive hardware design of boosting compression

Premachand¹,

Eranna²

2021

IJECE

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Performing the image compression over the resource constrained hardware is quite a challenging task. Although, there has been various approaches being carried out towards image compression considering the hardware aspect of it, but still there are problems associated with the memory acceleration associated with the entire operation that downgrade the performance of the hardware device. Therefore, the proposed approach presents a cost effective image compression mechanism which offers lossless compression using a unique combination of the non-linear filtering, segmentation, contour detection, followed by the optimization. The compression mechanism adapts analytical approach for significant image compression. The execution of the compression mechanism yields faster response time, reduced mean square error, improved signal quality and significant compression ratio performance.

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Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications

Cited by 12 publications

References 28 publications

Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

Time–frequency localization using three-tap biorthogonal wavelet filter bank for electrocardiogram compressions

Novel hybrid framework for image compression for supportive hardware design of boosting compression

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