Algorithm development for a digital optical processor

Abstract

The digital optical logic unit described here consists of two Semetex 48 by 48 element Sight-Mods, the pixel pattern from one being imaged on the second. Since the allowed pixel states are binary, the output from these modulators can have three possible states. We describe the practical difficulties associated with digital computing using hardware of this kind, including camera readout and thresholding procedures. Once the three level output has been captured, it can be interpreted directly to yield simple logical relationships between adjacent pixels. The execution of more complicated operations such as addition and multiply have been studied and algorithms developed, which can exploit the paralellism of the spatial light modulators. We describe these algorithms, identify the computational bottlenecks and discuss the potential such a system might attain. The latter obviously depends on eventual hardware capabilities, but novel exploitation of parallel addressing schemes and better use of the available three level output states offer new and different opportunities for improved computational performance.