Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA

Kenter, Tobias; Shambhu, Adesh; Faghih-Naini, Sara; Aizinger, Vadym

doi:10.1145/3468267.3470617

Cited by 9 publications

(1 citation statement)

References 20 publications

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“…It bundles a number of other numerical and computational techniques such as a novel block-structured grid generator for ocean domains (Zint et al 2019(Zint et al , 2022Faghih-Naini et al 2022) and the code generation framework (Lengauer et al 2014;Schmitt et al 2014a;Kuckuk and Köstler 2016). Our future research goals include adding the FPGA support-already available for the unstructured-mesh version of the model (Kenter et al 2021;Faj et al 2023)-and implementing semi-implicit time stepping schemes based on the hierarchical scale separation (HSS) approach (Aizinger et al 2015;Schütz and Aizinger 2017) related to the p-multigrid method.…”

Section: Discussionmentioning

confidence: 99%

p-adaptive discontinuous Galerkin method for the shallow water equations with a parameter-free error indicator

Faghih-Naini

Aizinger

2022

Int J Geomath

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We propose a p-adaptive quadrature-free discontinuous Galerkin method for the shallow water equations based on a computationally efficient adaptivity indicator which works without any problem-dependent parameters. The error and smoothness of the solution are detected using the information collected for slope limiting and, for piecewise constant discretizations, by carrying out a reconstruction procedure. The accuracy and robustness of the new scheme are evaluated using several benchmarks and compared to other adaptivity indicators. Our results indicate that the proposed indicator finds a good balance between solution quality and computational overhead.

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Section: Discussionmentioning

confidence: 99%

p-adaptive discontinuous Galerkin method for the shallow water equations with a parameter-free error indicator

Faghih-Naini

Aizinger

2022

Int J Geomath

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Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline

Alt,

Kenter,

Faghih-Naini

et al. 2023

Lecture Notes in Computer Science

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Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL

Meyer,

Kenter,

Petrica

et al. 2024

Lecture Notes in Computer Science

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Most FPGA boards in the HPC domain are well-suited for parallel scaling because of the direct integration of versatile and high-throughput network ports. However, the utilization of their network capabilities is often challenging and error-prone because the whole network stack and communication patterns have to be implemented and managed on the FPGAs. Also, this approach conceptually involves a trade-off between the performance potential of improved communication and the impact of resource consumption for communication infrastructure, since the utilized resources on the FPGAs could otherwise be used for computations. In this work, we investigate this trade-off, firstly, by using synthetic benchmarks to evaluate the different configuration options of the communication framework ACCL and their impact on communication latency and throughput. Finally, we use our findings to implement a shallow water simulation whose scalability heavily depends on low-latency communication. With a suitable configuration of ACCL, good scaling behavior can be shown to all 48 FPGAs installed in the system. Overall, the results show that the availability of inter-FPGA communication frameworks as well as the configurability of framework and network stack are crucial to achieve the best application performance with low latency communication.

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Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA

Cited by 9 publications

References 20 publications

p-adaptive discontinuous Galerkin method for the shallow water equations with a parameter-free error indicator

p-adaptive discontinuous Galerkin method for the shallow water equations with a parameter-free error indicator

Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline

Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL

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