Algorithm-hardware co-design of ultra-high radix based high throughput modular multiplier

Abstract

This paper presents an algorithm-hardware co-design of ultrahigh radix modular multiplier for high throughput modular multiplication. First, to speed up the modular multiplication, we exploit an ultra-high radix interleaved modular multiplication algorithm with a novel segmented reduction method, which reduces the number of iterations and precomputations. Then, to further improve the throughput of the modular multiplication, we design a highly parallel modular multiplier architecture. Finally, we implement and verify the modular multiplier using the Xilinx Virtex-7 FPGA. Experimental results show it can perform a 256-bit modular multiplication in 0.56 µs with the throughput rate of up to 4999.7 Mbps.

FPGA-based high-throughput Montgomery modular multipliers for RSA cryptosystems

“…However, the cycle cost of serial multipliers are much higher than fullword multipliers. And thus, many designs [12,13,14,15,16,17,18,19] propose high-radix methods that scan multiple bits synchronically to reduce the cycle cost. Furthermore, to deal with the time-consuming carry chain of partial product accumulation, carry-save structures are adopted [14,18] to optimize the latency.…”