Algorithmic Design of an FPGA-Based Calculator for Fast Evaluation of Tsunami Wave Danger

Abstract

Events of a seismic nature followed by catastrophic floods caused by tsunami waves (the incidence of which has increased in recent decades) have an important impact on the populations of littoral regions. On the coast of Japan and Kamchatka, it takes nearly 20 min for tsunami waves to approach the nearest dry land after an offshore seismic event. This paper addresses an important question of fast simulation of tsunami wave propagation by mapping the algorithms in use in field-programmable gate arrays (FPGAs) with the help of high-level synthesis (HLS). Wave propagation is described by the shallow water system, and for numerical treatment the MacCormack scheme is used. The MacCormack algorithm is a direct difference scheme at a three-point stencil of a “cross” type; it happens to be appropriate for FPGA-based parallel implementation. A specialized calculator was designed. The developed software was tested for precision and performance. Numerical tests computing wave fronts show very good agreement with the available exact solutions (for two particular cases of the sea bed topography) and with the reference code. As the result, it takes just 17.06 s to simulate 1600 s (3200 time steps) of the wave propagation using a 3000 × 3200 computation grid with a VC709 board. The step length of the computational grid was chosen to display the simulation results in sufficient detail along the coastline. At the same time, the size of data arrays should provide their free placement in the memory of FPGA chips. The rather high performance achieved shows that tsunami danger could be correctly evaluated in a few minutes after seismic events.

Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm

“…Once these topics are dominated, the HLS approach provides quite substantial productivity gains over RTL design. This conclusion is in concordance with related works [25][26][27][28], where the authors point out that the HLS method contributes to accelerating the development of data processing algorithms, but also that engineers need to dominate technologies of parallel programming and possess/acquire knowledge about the structure and features of FPGA. Moreover, HLS usually permits individual components to be synthesized that must be further integrated at the RT level, implying that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS [29].…”

Field Programmable Gate Array-Based Acceleration Algorithm Design for Dynamic Star Map Parallel Computing

“…In this paper, an FPGA-based algorithm for displaying star charts of a dyn simulator is designed that can output star charts under the condition that the s field of view is 20   and the simulated magnitude is 2.0 6.0 Mv . (1) The article analyzes the calculation of the optical axis pointing calculat the optical axis pointing coordinate transformation calculation part, the star are range calculation part, the star point coordinate transformation calculation part Table 5 shows the comparison of the performance of different methods for star chart computation.…”

“…The main clock of the FPGA chip is 50 MHz, and the 148.5 MHz pixel clock is used in the calculation module [20]. There is a process of transmitting data across the clock domain in the communication, and it is necessary to add two levels of triggers to synchronize the signals for transmitting the data to prevent the phenomenon of race and hazard from occurring.…”