Algorithms for reducing reconfiguration overheads using prefetch, reuse, and optimal mapping of tasks

Abstract

Summary Field Programmable Gate Arrays (FPGAs) are preferred in the modern embedded system to accelerate the performance of the entire system. However, the FPGAs are liable to suffer from reconfiguration overheads. These overheads are mainly because of the configuration data being fetched from the off‐chip memory at run‐time and due to the improper management of tasks during execution. To reduce these overheads, two algorithms are proposed. Both the algorithms focus on the prefetch heuristics, reuse technique, and an optimal mapping of tasks over the available memories. However, in terms of reusing technique, algorithm‐1 uses least recently used (LRU) policy and algorithm‐2 uses the optimal replacement policy (considering the vitality of the reconfigurable units (RUs)). Simulation results are obtained for both the algorithms. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on the proposed algorithms. Also, the two algorithm results are compared and analyzed. For this purpose, the experiments included smaller and larger task graphs. In the case of smaller task graphs, algorithm‐2 outperforms algorithm‐1 in reducing reconfiguration overheads. In larger task graphs, algorithm‐1 produces better results compared to algorithm‐2.

A Survey: FPGA‐Based Dynamic Scheduling of Hardware Tasks

“…When there is no reusable task module and no configuration space, the task is migrated to the software processing unit for execution. Similar work is also a scheduling algorithm proposed by Hariharan and Kannan [ 26 ] that uses LRU and optimal replacement strategy. They try to avoid using software processing units and pay more attention to using more efficient hardware resources to process all tasks.…”

“…Table 1 (Refs. [15,16,18–22,25–42,45–49,51–55,57–70]) lists the research work done by researchers for different optimization goals in each time period. During the period 20002005, 9 papers were published.…”

“…From the perspective of ensuring the universality of FPGA accelerators, Jiang et al [75] and Ma et al [76] designed scheduling strategies that can apply to neural networks of different types and different precision. Banerjee [15] √ − − × Marconi [45] − × √ − Resano [16] √ − − × Tabero [46] − √ √ − Khuat [18] √ − √ × Marconi [47] − √ √ − Ramezani [19] √ − − × Xu [48] − √ √ − Bauer [20] √ − − × Enemali [49] √ − √ − Dai [21] √ − √ × Diessel [51] × − √ × Cattaneo [22] √ − √ × Gericota [52] × − √ × AlWattar [25] √ − − × George [53] × × √ × Hariharan [26] √ − − × MoralesVillanueva [54] × × √ × Mansub [27] √ − √ √ Enemali [55] − − √ − Deiana [28] √ − − × Yuh [57] √ − − √ Fekete [29] − √ − − Li [58] √ − − √ Marconi [30] − √ − − Hsieh [59] √ − − √ Cadi [31] √ √ − − Pham [60] √ − − √ Abdallah [32] √ √ − − Wang [61] √ − − √ Ahmadinia [33] − √ − − Pham [62] √ − − √ Sheng [34] − √ − − Zhou [63] √ − − √ Huang [35] − √ √ × Ghorbani [64] − − − √ Yoosefi [36] − √ − − Khodabandeloo [65] √ − − √ Bazargan [37] − − √ − Yang…”