Algorithms for the Accounting of Multiple Switching Events in Digital Simulation of Power-Electronic Systems

Abstract

Digital simulation of power systems containing power electronics apparatus is challenging due to the need to account multiple switching events within one simulation time-step. This paper describes a family of algorithms, with varying levels of computational complexity, for accounting such switching events in digital simulations. The proposed algorithms are applicable for both off-line and real-time simulations. A comparative study on their performance such as harmonic content, errors in fundamental component and simulation time requirement is presented. A Pulse Width Modulated (PWM) Voltage Source Converter (VSC) based D-STATCOM system is used as a case study for simulations. Simulation results indicate excellent performance (accuracy and efficiency) in comparison with a fixed time-step algorithm using a small step-size.

A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing

“…Addressing multiple switching events, based on these corrective measures [25], result in a significant computational burden since multiple interpolations/extrapolations within each simulation timestep are required which in turn can limit or even violate real-time calculation requirements [26]. In this work, the proposed FPGA-based real-time simulator utilizes a massively parallel, customized, hardware architecture that is specifically designed to allow the real-time simulation of power electronic systems with timesteps significantly smaller than those of existing real-time simulators, e.g., tens to few hundreds of nanoseconds.…”

A new versatile hardware platform for digital real-time simulation: Verification and evaluation

“…Various algorithms for the accounting of internal or external MITS events on controlled or uncontrolled devices are presented in [13] and [14]. The latter presents a comprehensive overview of algorithms to handle MITS events.…”

“…In general, avoiding multiple integration inside the same time step is a suitable approach to keep calculation time low and deterministic in real-time applications. In this context the algorithms proposed in [13] and [14], based on interpolation and extrapolation, are much more interesting as additional overhead required by the these algorithms is typically very limited. Moreover, the use of algorithms with multiple integrations offers significant benefit only when a large time step size compared to the switching frequency is used, as shown in [14].…”

“…In this context the algorithms proposed in [13] and [14], based on interpolation and extrapolation, are much more interesting as additional overhead required by the these algorithms is typically very limited. Moreover, the use of algorithms with multiple integrations offers significant benefit only when a large time step size compared to the switching frequency is used, as shown in [14]. A significant benefit of the approach proposed in [13] is that does not assume that the time at which the ITS occurs is known.…”

“…The proposed approach, as all the methods proposed in [14], implies that the external signals are acquired through the use of an FPGA or any other additional processor that samples the input with a very high frequency compared to the simulation time-step. The method proposed in [15] uses a converter model which is averaged over the simulation time step.…”