Aliasing errors in linear automata used as multiple-input signature analyzers

Daehn, Wilfried; Williams, T.W.; Wagner, K.D.

doi:10.1147/rd.342.0363

Cited by 38 publications

(8 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the independent error model (e.g. [16]), error bits at different outputs of the CUT are statistically independent and can have different probabilities. The more general error model of [17] and [18] specifies the probabilities of all the 2 possible error patterns individually.…”

Section: Definitionmentioning

confidence: 99%

Signature Analysis for Test Responses of Sequential Circuits

Stroele

1998

VLSI Design

View full text Add to dashboard Cite

Many test schemes use signature analyzers to compact the responses of a circuit under test. Unfortunately, there can be some faulty circuits with erroneous test responses but exactly the same signature as in the fault-free case. Hence, methods are required to determine how many faults become undetectable due to aliasing. Whereas previous work concentrated on combinational circuits, this paper investigates signature analysis for a wide range of sequential circuits, where the errors in successive responses are correlated. It is shown that for almost all faults of these circuits the probability of aliasing in a signature analyzer with k bits asymptotically approaches 2−k or is 0 if a signature analyzer with an irreducible characteristic polynomial is used and certain test lengths are avoided. The limiting value can be used as a good approximation for practical test lengths. These results are particularly useful for advanced built-in self-test techniques with low hardware overhead.

show abstract

Section: Definitionmentioning

confidence: 99%

Signature Analysis for Test Responses of Sequential Circuits

Stroele

1998

VLSI Design

View full text Add to dashboard Cite

show abstract

“…The problem of computing the aliasing probability in SISRs and MISRs has been considered by many researchers [4,28,29,30]. Different assumptions were used by different researchers regarding the behavior of errors entering the signature registers.…”

Section: Signature Registersmentioning

confidence: 99%

Built‐In Self‐Test: Milestones and Challenges

Savir

Bardell

1993

VLSI Design

View full text Add to dashboard Cite

show abstract

“…There have been numerous papers published on aliasing by linear compactors [7]- [15] and on aliasing by counters [1], [4], [5], [16], [17]- [19]. Most early results [4], [17]- [18], [20] were based on the assumption that, for a faulty CUT, all compactor input sequences were equally likely.…”

Section: Introductionmentioning

confidence: 99%

Counter-based compaction: An analysis for BIST

Pilarski

Wiebe

1992

J Electron Test

View full text Add to dashboard Cite

According to some recently published results, counter-based compaction outperforms compaction by linear feedback shift registers. These results, however, are based on oversimplified assumptions. In this paper, we discuss an error model to describe the behavior of a faulty circuit under test. We study the three most popular counter-based compaction schemes, (i.e., one's counting, transition counting and edge counting). Using Markov processes we derive equations for iterative computations of exact aliasing probability for any test session length and determine the asymptotic probability of aliasing. For one's counting, we also present a closed form expression that, for any test session length, gives the exact aliasing probability. Finally, we present some examples to compare the aliasing in the counter-based compaction and compaction by a linear feedback shift register. These examples indicate that aliasing by LFSRs is more "predictable" than aliasing by counters.

show abstract

Aliasing errors in linear automata used as multiple-input signature analyzers

Cited by 38 publications

References 18 publications

Signature Analysis for Test Responses of Sequential Circuits

Signature Analysis for Test Responses of Sequential Circuits

Built‐In Self‐Test: Milestones and Challenges

Counter-based compaction: An analysis for BIST

Contact Info

Product

Resources

About