Aliasing-free compaction revisited

Abstract

The design of space-efficient support hardware for built-in self-testing is of immense significance in the synthesis of present day very large-scale integration circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). The authors revisit the general problem of designing zero-aliasing (or aliasing-free) space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of conventional switching theory and of incompatibility relation to generate maximal compatibility classes utilising graph theory concepts, based on optimal generalised sequence mergeability, as developed by them in earlier works. The authors briefly present the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test for realising maximum compaction ratio in the design, along with extensive simulation results on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM and COMPACTEST.