Alignment system and process optimization for improvement of double patterning overlay

Ma, Won-Kwang; Kang, Jung-Hyun; Lim, Chang-Moon; Kim, HyeongSoo; Moon, Seung-Chan; Lalbahadoersing, S.; Oh, Seung-Chul

doi:10.1117/12.772474

Cited by 4 publications

(3 citation statements)

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“…We assumed that α is 3nm, φ is ± 0.05 µ radian, M is ± 0.05ppm, and metal spacing without overlay is 48nm. This assumption is reasonable at 3-σ level [2]. We calculated the delay along the translation angle as shown in Figure 15.…”

Section: Capacitancementioning

confidence: 78%

“…second lithography steps. The advanced lithography equipment has about 5nm of overlay in 3-σ level which is relatively large compared with 32nm half pitch size [2], [3]. Since overlay may change the circuit behavior such as timing, noise, and power due to the distortion of layout pattern, we need a methodology to estimate the variation due to overlay during design.…”

Section: Introductionmentioning

confidence: 99%

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Overlay aware interconnect and timing variation modeling for Double Patterning Technology

Yang

Pan

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, we present an efficient modeling of timing variation with overlay which is inevitable for DPT. Our work makes it possible to analyze timing with overlay variables. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. To verify our work, we use identical interconnects having different positions and different layout decompositions. Experimental result shows that the delay has a variation from 7.8% to 9.1% depending on their locations. The well decomposed structure shows only 2.7% delay variation.

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Section: Capacitancementioning

confidence: 78%

Section: Introductionmentioning

confidence: 99%

Overlay aware interconnect and timing variation modeling for Double Patterning Technology

Yang

Pan

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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“…We have evaluated the impact of critical dimension control and overlay control [12][13][14] in the exposure tool by studying both the LELE and the LFLE double patterning. We report the results from an XT1700i and XT1900i exposure tools.…”

Section: Impact Of Exposure Tool On Double Patterningmentioning

confidence: 99%

Progress in Extending Immersion Lithography for the 32 nm Node and Beyond

Sewell¹,

Chen²,

Finders

et al. 2009

jjap

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Weak localization, a semiclassical process established in disordered systems, has recently been used as an experimental probe of the classical dynamics of ballistic cavities. Through a systematic study of the classical and quantum behaviour of three ballistic cavities featuring large width to length aspect ratios, we highlight the important role of the entrance and exit leads. We present a novel ballistic weak localization process in which the contributing classical trajectories pass directly between the entrance and exit leads and are not shaped by the walls of the cavity but purely by the profiles of the leads. This demonstration of a small section of a cavity supporting a 'local' weak localization process has important implications for studies which relate cavity geometry to the dynamics it supports.

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