All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores

Abstract

The Internet-of-Things (IoT) revolution fueled new challenges and opportunities to achieve computational efficiency goals. Embedded devices are required to execute multiple applications for which a suitable distribution of the computing power must be adapted at run-time. Such complex hardware platforms have to sustain the continuous acquisition and processing of data under severe energy budget constraints, since most of them are battery powered. The state-of-the-art offers several ad-hoc contributions to selectively optimize the performance considering aspects like energy, power, thermal or reliability. However, there is a need for a generic coordinated management strategy able to cope with all of these dimensions, while allowing the Operating System (OS) and the applications to "suggest" or constrain the actuation. This paper proposes a unified control-theoretic scheme to coordinate the design of energy-budget and energy allocation solutions for multi-cores. The proposed controller can work with any actuator and it can interact, at run-time, with both the applications and the OS to optimize the actuation signals steering the computing platform. Such control scheme offers the possibility to integrate any performance related policy in the form of an energy-allocation strategy, still ensuring the theoretic exponential stability of the overall controller if the actuation of the policy, coming from the OS and the applications, "is not too fast". To demonstrate the feasibility of our solution, we implemented the controller into a RISC multi-core running on the Xilinx Artix 100t FPGA device, available in the the Digilent Nexys4-DDR board. Results considering two actuators and both the quad-and the eight-core version of the considered computing platform, highlight the scalability of the proposed solution as well as an area overhead for the-all digital, on chip-controller limited to 0.86% (FFs) and 5.3% (LUTs) of the FPGA chip. We also considered a dynamic scenario validating the speed of the controller, where our framework has to face with modifications to the energy-allocation control policy carried out by the OS and the applications. The obtained results are collected by executing a huge mix of benchmarks and the statistical significance is accounted by executing each scenario 30 times. Such results are analyzed considering three quality metrics. First, the efficiency in exploiting the imposed budget (EF Fg) that is on average 98.27%. Second, the overflow of the actual average power consumption with respect to the assigned budget (OV Fg), which is limited to 1.43 mW on average. Last, the performance utility loss due to the control scheme that is limited to 1.87% on average.

TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale

“…Energy efficiency can then be guaranteed only if, on the SW side, we can rely on a suitable (hierarchical) resource management framework. Although the state-of-theart already includes some solutions, recent projects, like MANGO [28] and RECIPE [29], show that optimized solutions need to take into account the platform-specific characteristics and control knobs to profile the applications at design-time and monitor them at runtime [30], [31], enabling more accurate resource mappings [32], [33]. Furthermore, an integration of the resource manager with the programming model allows dynamically tuning the numerical accuracy (precision) of the tasks, with respect to the actual application requirements and power/energy constraints.…”

“…Given the reference HW platform and the application use cases, the TEXTAROSSA project would represent an extremely interesting testbed for exploring novel power and energy management solutions, at the HW but also at the SW level. At the HW level, a specific support will be introduced to automatically instrument the computing platform with ad-hoc power monitors [34] and controllers [30], [31], in order to reduce the response time of the power management dramatically, while increasing the effectiveness of the thermal management. On the software side, starting from an already existing resource management framework [35], we aim to extend it with the support for the new HW and, of course, new resource management policies, along with the integration of the precision tuning tool.…”

Cost-effective fixed-point hardware support for RISC-V embedded systems

“…Modern embedded systems, especially those at the edge, are no longer only smart sensors but also general-purpose computing platforms in charge of efficiently performing a large variety of computationally intensive tasks. Apart from using systemwide energy-performance optimization policies [1,2] employing run-time power monitors either in hardware [3] or software [4], a vast amount of research targets the optimization of the floating-point computations executed in such tasks. Approximate computing techniques operate at compile-time to leverage the error tolerance of several emerging applications by trading the accuracy of the computed data with their energy consumption [5].…”

An FPU design template to optimize the accuracy-efficiency-area trade-off

“…Modern embedded systems, especially those at the edge of the computing continuum, are no longer only smart sensors, but also general-purpose computing platforms performing data-processing, for which the computational efficiency is a standing design requirement. To this end, the design of (i) efficient hardware accelerators [1,2] and (ii) run-time energy-performance strategies [3] represents the de-facto solution to cope with the requirements of these new workload scenarios. In particular, such workloads are strongly heterogeneous, encompassing both critical and best-effort classes of applications.…”