All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application

Abstract

A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-µm standard complementary metal oxide semiconductor process with a core area of 0.091 mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40–60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps.

Duty Cycle Corrector Using Pulse Width Modulation

“…The motivation behind this work was, usage of single stage amplifier requires large gain making it sensitive to VDD, hence the author proposed this two stage structure. In [11], a synchronous all digital DCC is presented. It uses dual loop feedback, one corrects the duty cycle and other corrects the skew between input and output clock.…”