All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

Ogasahara, Yasuhiro; Hashimoto, Masanori; Onoye, Takao

doi:10.1109/jssc.2009.2020192

Cited by 35 publications

(17 citation statements)

References 24 publications

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“…Traditional oscillation sampling method [3] uses a low frequency clock to sample a high frequency clock. The output of the sampling value is random number sequence.…”

Section: Design Of True Random Number Generatormentioning

confidence: 99%

A Low Power True Random Number Generator in 0.18 M CMOS

Huang¹,

Li²,

Wan³

2017

Proceedings of the International Conference on Communication and Electronic Information Engineering (CEIE 2016)

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This paper presents the design and implementation of a true random number generator (TRNG) for smart card application. Based on the effect of the oscillator phase noise and meta-stable state of the trigger, the random number is generated. An efficient calibration method can correct the uniformity of random number sequences and improve the distribution of the random number. The prototype of the TRNG is fabricated in a 0.18μm CMOS technology. Under the standard diehard test, the results show that bit rate is 1Mb/s and the TRNG has a good pass rate under a bad condition. The power consumption of the TRNG is 0.066mW with a 1.8V power supply.

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“…Traditional oscillation sampling method [3] uses a low frequency clock to sample a high frequency clock. The output of the sampling value is random number sequence.…”

Section: Design Of True Random Number Generatormentioning

confidence: 99%

A Low Power True Random Number Generator in 0.18 M CMOS

Huang¹,

Li²,

Wan³

2017

Proceedings of the International Conference on Communication and Electronic Information Engineering (CEIE 2016)

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“…4(b) [11] is adopted. The test chip fabrication technology is the same as that reported in [11], and the time and voltage resolutions of this macro are, respectively, about 180 ps and 10 mV. Fig.…”

Section: B Teg Structurementioning

confidence: 99%

Supply Noise Suppression by Triple-Well Structure

Ogasahara

Hashimoto

Kanamoto

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-This brief discusses the impact of twin-and triplewell structures on power supply noise, and a substrate model for simulating the power supply noise. We observed V ss noise reduction by the resistive network of the p-substrate and V dd noise reduction by the junction capacitance of a triple-well structure on a 90-nm test chip. Measurement results also showed that the total noise reduction of a triple-well structure is superior to that of a twin-well structure. The measurement results correlate well with the results obtained from the power supply noise simulation using a hierarchical resistive mesh model. Our simulation-based verification indicates that in common CMOS design, a triplewell structure can reduce the power supply drop by 10%-40% or the decoupling capacitance area by 5%-10%. We also verified that supply drop sensitivity to variation of the well junction capacitance is sufficiently small and that supply noise reduction using a triple-well structure is robust to process variation.Index Terms-Circuit noise, noise measurement, substrate.

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“…The shift registers store configurations of the TEGs. The counter used in the waveform sampling macro [6] is also included in the shift resistors. This macro called "gated oscillator" is a ring-oscillatorbased circuit but it captures dynamic noise waveforms thanks to intermittent operation at the timing of interest.…”

Section: A Test Chip Structure 1) Overviewmentioning

confidence: 99%

“…The switch for power gating is repeatedly turned on and off in every 50 nano seconds (10MHz). Due to the limitation of the noise measurement macro [6], a slower operation is difficult. Since the power gating period of 50 nano seconds is not long enough to discharge the capacitance in gated NS, we gave a pulse to make gated NS run during the period of power gating and discharged the capacitance.…”

Section: A Evaluation Setupmentioning

confidence: 99%

Evaluation of power gating structures focusing on power supply noise with measurement and simulation

Takai

Hashimoto

Onoye

2010

19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

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Abstract-This paper investigates the impact of power gating structure on power supply noise using 65nm test chip measurement and simulation. We focus on the body connection of power-gated circuits, and examine the contribution of a powergated circuit as a decoupling capacitance during the sleep mode. Experimental results show that the well junction capacitance of the power-gated circuit with body-tied structure helps reduce power supply noise while a sharp drop cannot be mitigated due to its large RC time constant.

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All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

Cited by 35 publications

References 24 publications

A Low Power True Random Number Generator in 0.18 M CMOS

A Low Power True Random Number Generator in 0.18 M CMOS

Supply Noise Suppression by Triple-Well Structure

Evaluation of power gating structures focusing on power supply noise with measurement and simulation

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