All-digital thermal distribution measurement on field programmable gate array using ring oscillators

Yuan, Yue; Feng, Shiwei; Guo, Chunsheng; Yan, Xiao-Bo; Feng, Ruirui

doi:10.1016/j.microrel.2014.10.010

Cited by 12 publications

(5 citation statements)

References 11 publications

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“…In this study, the performance of RO-PUF subsequent to temperature changes will be observed. The frequency of RO decreases when the temperature is increased [20,47,48]. Therefore, this work calculated reliability based on the consistency of pulses at different temperatures according to Equations ( 2) and (3), where k is the number of experiments on the same chip, R s is the response bit from chip i at low temperature, R s,t is the t-th sample of R' s response bit from chip i at a higher temperature.…”

Section: Ro-puf Metricmentioning

confidence: 99%

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

et al. 2021

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The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF.

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Section: Ro-puf Metricmentioning

confidence: 99%

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

et al. 2021

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“…Some designs are based on the built-in thermal diode [3], [4] which use the system monitor in Xilinx FPGAs and intellectual property (IP) cores in Altera FPGAs [18]. Among other alternative methods, some designers utilize external devices such as temperature probe, oven, and chamber which are applied as a reference for calibration [7], [9].…”

Section: B Sensor Calibrationmentioning

confidence: 99%

“…In the last years, the designers have paid a lot of attention to soft sensors. They have proposed different designs for soft sensors [5][6][7][8][9][10][11][12][13][14][15][16][17]. Some researchers utilize an array of temperature sensors based on a ring oscillator (RO).…”

Section: Introductionmentioning

confidence: 99%

Exploration of ring oscillator based temperature sensors network accuracy on FPGA

Korkian

Rahmanikia

Noori

et al. 2017

2017 19th International Symposium on Computer Architecture and Digital Systems (CADS)

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During the last decades, technology scaling in reconfigurable logic devices enabled implementing complicated designs which results in higher power density and on-chip temperature. Since higher operating temperature of chips is a critical problem in electronics devices, thermal management techniques are highly required. To provide a thermal map of reconfigurable logic devices, a network of sensors is needed. In this work, a ring-oscillator-based temperature sensor is used to create a sensor network. Then, a design space exploration is done among several sensor networks with the various sensor configurations including different ring oscillator length, the number of sensors in the examined network and various sampling time. We propose three criteria for exploring and comparing the efficiency of sensors network based on the thermal overhead and also measurement accuracy and precision among plenty of configurations on the Virtex-6 FPGA.

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“…Currently, Field Programmable Gate Array (FPGA) chips have been used many areas since they have advantages like parallel processing, reconfigurablity, high speed comparable to other HardWare (HW) systems, possibility of the verification the designs by testing before the implementation of the HW, very low-cost than Application Specific Integrated Circuits (ASIC) HW for prototyping. Control [1], sensors [2], image processing [3], signal processing [4], converter systems [5], computer graphics [6], medicine [7], radio frequency systems [8], Artificial Neural Networks (ANNs) [9] are among the usage areas of FPGAs. ANNs, which are one of the research areas of FPGAbased HW, are parallel information processing systems in their nonlinear structure.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of High Speed Artificial Neural Network Based Sprott 94 S System on FPGA

Koyuncu

2016

Int J Intell Syst Appl Eng

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FPGA-based embedding system designs have been preferred for industrial applications and prototyping because of the advantages of parallel processing, reconfigurability and low cost. Due to having characteristic structure of the parallel processing of Artificial Neural Networks (ANNs), these systems provide the advantage of speed and performance when they are implemented with FPGA-based hardware. The hardware implementation of transfer functions used for modeling non-linear systems is a challenging problem. Therefore, this problem creates convergence problems. In this paper, non-linear Sprott 94 S system has been modeled using ANNs running on FPGA. All related parameter values and processes are defined with IEEE-754-1985 32-bit single precision floatingpoint number standard. ANN-based Sprott 94 S system design has been developed using VHDL synthesized using Xilinx ISE Design Tools. In test stage, ANN-based Sprott 94 S system has been tested using 3X100 data set and obtained error analysis results have been presented. The constructed design has been performed for Xilinx VIRTEX-6 family XC6VHX255T-3FF1923 FPGA chip using Place&Route process and chip usage statistics have been given. The clock frequency of ANN-based Sprott 94 S system which has pipeline processing scheme has been obtained with the value of 304.534 MHz. Accordingly, the proposed FPGA-based ANN system has produced 3X3.284 billion outputs in 1 second.

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All-digital thermal distribution measurement on field programmable gate array using ring oscillators

Cited by 12 publications

References 11 publications

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

Exploration of ring oscillator based temperature sensors network accuracy on FPGA

Design and Implementation of High Speed Artificial Neural Network Based Sprott 94 S System on FPGA

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