All-hardware SIFT implementation for real-time VGA images feature extraction

Doménech‐Asensi, G.; Zapata, Juan; Ruiz‐Merino, Ramón; Lopez-Alcantud, J. A.; Díaz‐Madrid, José Ángel; Brea, V.M.; López, P.

doi:10.1007/s11554-018-0781-0

Cited by 7 publications

(6 citation statements)

References 6 publications

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“…Our solution can process a 480 px × 480 px resolution image which has a higher resolution compared to the Chang et al 19 and Shao et al, 20 but Doménech-Asensi et al 15 and Vourvoulakis et al 17,18 implementations can process images with higher resolution of 640 px × 480 px. Our proposed architecture can compute 135 frames per second, which is higher than both Doménech-Asensi et al 15 and Vourvoulakis et al 17,18 and Shao et al 20 In comparison, Chang et al 19 solution can process 900 frames per second; however, it uses lower image resolution. Our implementation is a software/hardware Note: The Intel Xeon E5-2620 and ARM Cortex-A53 are used the OpenSIFT12 and the Xilinx UltraScale+ ZCU102 are used our FPGA implementation.…”

Section: Comparison Of the Different Fpga Implementationsmentioning

confidence: 93%

“…There are CPU, 11,12 GPU 13,14 and FPGA implementations. [15][16][17][18][19][20] The OpenCV SIFT library 11 and the OpenSIFT 12 are popular frameworks for SIFT keypoint extraction and descriptor computation in CPUs. This is partially due to their flexibility as the input image resolution can be modified easily.…”

Section: Related Workmentioning

confidence: 99%

“…Several different SIFT implementations on FPGA are published such as the system designed by Doménech-Asensi et al, 15 which is a simplified version of the algorithm. It is assumed that each feature point has two main orientations at most, the orientation histogram uses 8 bins instead of 36 bins.…”

Section: Related Workmentioning

confidence: 99%

“…As Table 7 indicated we used a different FPGA board (Xilinx UltraScale+ ZCU102) from that used in previous studies. Doménech-Asensi et al 15 and Shao et al 20 use Xilinx Virtex-5. Rubio-Ib añez et al 16 implementation run on Zedboard, and Vourvoulakis et al 17,18 developed their solution on Intel DE2i-150.…”

Section: Comparison Of the Different Fpga Implementationsmentioning

confidence: 99%

“…solution similarly to Rubio-Ib añez et al, 16 and Chang et al 19 and Shao et al 20 Other papers such as Doménech-Asensi et al 15 and Vourvoulakis et al 17,18 use solutions that are a hardware but simplified implementation of the SIFT, which impacts the algorithm accuracy. Our solution is using a float number representation instead of the fixed-point representation.…”

Section: Comparison Of the Different Fpga Implementationsmentioning

confidence: 99%

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Implementation of Scale Invariant Feature Transform detector on FPGA for low‐power wearable devices for prostheses control

Fejér

Nagy

Benois‐Pineau

et al. 2021

Circuit Theory & Apps

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In this paper we describe an FPGA implementation of the Scale Invariant Feature Transform (SIFT) algorithm. The FPGA is required as its a lightweight device which makes it ideal for vision-guided hybrid neuro-prostheses utilised for upper limbs replacement. SIFT point detection is needed for computation of coordinates of the object-to-grasp in a wearable multi-camera system. A modified SIFT algorithm is proposed and an implementation of it into C/C++ language on Xilinx ZCU102 FPGA board. The proposed hybrid hardware/ software solution is compared to other hardware or hybrid implementations of the SIFT algorithm and with the baseline software detector OpenSIFT. The algorithm optimised for FPGA gives an average precision of 0.84 and the average recall of 0.94 in SIFT-point detection compared to the baseline.The proposed solution has lower dissipated power than other solutions like CPU or GPU, and it has better computational speed. This solution allows for processing medium-sized images in real-time with low power consumption.

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