All-SiC Module Packaging Technology

Shirata, Kento; Nashida, Norihiro; Nakamura, Hideyo; Nishimura, Yoshitaka

doi:10.23919/ipec.2018.8507946

Cited by 1 publication

(1 citation statement)

References 4 publications

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“…As shown in Figure 5a, Fuji Electric has developed a copper pin interconnection structure to replace traditional wire bonding, combined with a silver-sintering process, significantly reducing the overall thermal resistance of SiC devices. Compared to traditional Si-based wire bonding interconnections, the overall thermal resistance is reduced by 50%, and the losses are decreased by 57-87% [33]. Mouawad, considering compact paths and effective heat management under a high power density, has proposed a highly integrated planar multi-chip 10 kV SiC MOSFET design based on stacked substrates and embedded technology, offering a strong packaging flexibility, as shown in Figure 5b.…”

Section: Sic Power Device With a Low-thermal-resistance Package Designmentioning

confidence: 99%

Review on Power Cycling Reliability of SiC Power Device

Gao,

Jia,

Wang

et al. 2024

Electronic Materials

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The rising demand for increased integration and higher power outputs poses a hidden risk to the long-term reliable operation of third-generation semiconductors. Thus, the power cycling test (PCT) is widely regarded as the utmost critical test for assessing the packaging reliability of power devices. In this work, low-thermal-resistance packaging design structures of SiC devices are introduced, encompassing planar packaging with dual heat dissipation, press-pack packaging, three-dimensional (3D) packaging, and hybrid packaging. PCT methods and their control strategies are summarized and discussed. Direct-current PCT is the focus of this review. The failure mechanisms of SiC devices under PCT are pointed out. The electrical and temperature-sensitive parameters adopted to monitor the aging of SiC devices are organized. The existing international standards for PCT are evaluated. Due to the lack of authoritative statements for SiC devices, it is difficult to achieve comparison research results without consistent preconditions. Furthermore, the lifetimes of the various packaging designs of the tested SiC devices under PCTs are statistically analyzed. Additionally, problems related to parameter monitoring and test equipment are also summarized. This review explores the broader landscape by delving into the current challenges and main trends in PCTs for SiC devices.

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Section: Sic Power Device With a Low-thermal-resistance Package Designmentioning

confidence: 99%