All-solid-state Ion Synaptic Transistor for Wafer-scale Integration with Electrolyte of a Nanoscale Thickness

Abstract

Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation, and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with the large number of conductance levels are required. Here an all-solid-state polymer electrolyte-gated synaptic transistor (pEGST) was fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition (iCVD) process. The pEGST showed good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ/pulse. Selected 128 levels from 8,192 used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7 %.

Flexible and Energy-Efficient Synaptic Transistor with Quasi-Linear Weight Update Protocol by Inkjet Printing of Orientated Polar-Electret/High-k Oxide Composite Dielectric

“…The ultrashort pulse stimulus is attributed to the fast response of dipole inversion on the aligned PVP chains. As indicated in Figure g, the recognition accuracy and the energy consumption are comparable or superior to most of the reported synaptic transistors. ,,,,,,− Table S3 presents a statistical comparison of several typical synaptic transistors. The quality of the data set adopted in this work is appropriate for the comparison, when considering the same database used for the simulation and the detailed discussion of the key factors that affect the simulation of image recognition accuracy (nonlinearity and the dynamic range of the weight update).…”