All‐spin logic XOR gate implementation based on input interface

Wang, Sen; Yang, Ying; Song, Wenjing; Cui, Huanqing; Li, Cheng; Cai, Li

doi:10.1049/iet-cds.2018.5187

Cited by 8 publications

(4 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…If the channel length is more than spin diffusion length, then spin-flip would take place, hampering the functionality of ASL devices. There are various applications developed using ASL devices such as full adder [254,255], Boolean logic gates [255][256][257], and arithmetic logic unit [258]. A detailed review of ASL devices can be found in Refs.…”

Section: All Spin Logic Devicementioning

confidence: 99%

Spintronic devices: a promising alternative to CMOS devices

2021

View full text Add to dashboard Cite

The field of spintronics has attracted tremendous attention recently owing to its ability to offer a solution for the present-day problem of increased power dissipation in electronic circuits while scaling down the technology. Spintronic-based structures utilize electron’s spin degree of freedom, which makes it unique with zero standby leakage, low power consumption, infinite endurance, a good read and write performance, nonvolatile nature, and easy 3D integration capability with the present-day electronic circuits based on CMOS technology. All these advantages have catapulted the aggressive research activities to employ spintronic devices in memory units and also revamped the concept of processing-in-memory architecture for the future. This review article explores the essential milestones in the evolutionary field of spintronics. It includes various physical phenomena such as the giant magnetoresistance effect, tunnel magnetoresistance effect, spin-transfer torque, spin Hall effect, voltage-controlled magnetic anisotropy effect, and current-induced domain wall/skyrmions motion. Further, various spintronic devices such as spin valves, magnetic tunnel junctions, domain wall-based race track memory, all spin logic devices, and recently buzzing skyrmions and hybrid magnetic/silicon-based devices are discussed. A detailed description of various switching mechanisms to write the information in these spintronic devices is also reviewed. An overview of hybrid magnetic /silicon-based devices that have the capability to be used for processing-in-memory (logic-in-memory) architecture in the immediate future is described in the end. In this article, we have attempted to introduce a brief history, current status, and future prospectus of the spintronics field for a novice.

show abstract

Section: All Spin Logic Devicementioning

confidence: 99%

Spintronic devices: a promising alternative to CMOS devices

2021

View full text Add to dashboard Cite

show abstract

“…In particular, ASL does not require additional hardware for repeated spin-charge conversion, which has attracted considerable attention [11][12][13][14][15][16][17][18]. Various types of logic circuits based on ASL have been proposed, such as full adder [19], D flip-flop [20], RS flip-flop [21], and XOR gate [22]. However, as an important element in logic circuits, the decoder has not been reported in the public as much as we know.…”

Section: Introductionmentioning

confidence: 99%

Proposal of a 2-4 Decoder Based on All-spin Logic and Magnetic Tunnel Junction

Wang,

Zhang,

Shan

2024

Preprint

View full text Add to dashboard Cite

A 2–4 decoder based on all-spin logic (ASL) and magnetic tunnel junction (MTJ) is proposed. The proposed 2–4 decoder employs 5-input minority gates and single-input single-fan-out (SISF) structure. Meanwhile, the inverters are eliminated by initializing the magnetization of the MTJ fixed layer in different directions to realize the inputs of the original or inverse variables. To ensure that the proposed 2–4 decoder works properly, an asynchronous clock scheme is proposed, which divides the input signal into three phases and the operating voltage into two phases in one clock cycle. The operation of the proposed decoder is validated by the magnetization dynamics/spin transport self-consistent simulation framework, and the simulation results show that the delay and energy dissipation of the decoder are at the level of nanosecond and femtojoule, respectively. In addition, to illustrate the advantages of the 5-input minority gate, inverter-free structure, and SISF structures in the design of the proposed 2–4 decoder, a second 2–4 decoder is proposed using 3-input minority gates, inverters, and single-input multiple-fan-out structure. Compared with the second decoder, the layout area of the first decoder is reduced to 37.9%, the total channel length is reduced to 40.8%, the number of clock cycles is reduced to 1/3, and the energy dissipation is reduced by at least 3 orders of magnitude. Importantly, the design methods used in this work, such as multi-input minority gates, SISF structure, and inverter-free structure, provide an interesting approach for designing large-scale ASL logic circuits.

show abstract

“…But, fortunately, ASLD does not need extra hardware for implementing spin-charge conversion repeatedly, because spin is used at every stage of information processing, transfer, and storage [8]. Thus, ASLD is relatively simpler than other spintronic devices in structure and has been widely studied in the aspects of device switching mechanism [9][10][11], material and structural optimization [12][13][14][15][16][17][18][19][20][21][22][23], and circuit design [24][25][26].…”

Section: Introductionmentioning

confidence: 99%

Proposal for a spin logic device based on magneto‐electric effect and spin Hall effect

Wang

Zhang

et al. 2023

Micro & Nano Letters

Self Cite

View full text Add to dashboard Cite

Based on magneto-electric (ME) effect and spin Hall effect (SHE), the authors propose a novel spin logic device named MESH-SLD. In MESH-SLD, the charge current is transmitted in the channel by employing inverse SHE, which solves the dissipation problem of spin current in the channel of all-spin logic device (ASLD). By using a magnetizationdynamics/spin-transport hybrid model, the authors have investigated the influence of working voltage, channel lengths, and materials on the performance of the MESH-SLD. And the simulation results show that the energy dissipation of the MESH-SLD only increases approximately linearly with the increase of channel length, while the switching delay remains almost unchanged. In addition, with the increase of the spin Hall angle of the channel material, the energy dissipation and the minimum working voltage of the MESH-SLD decrease significantly. Most importantly, compared with conventional ASLD, the proposed MESH-SLD improve the switching delay and the energy dissipation by about 2.5 times and 851.8 times, respectively.

show abstract

All‐spin logic XOR gate implementation based on input interface

Cited by 8 publications

References 25 publications

Spintronic devices: a promising alternative to CMOS devices

Spintronic devices: a promising alternative to CMOS devices

Proposal of a 2-4 Decoder Based on All-spin Logic and Magnetic Tunnel Junction

Proposal for a spin logic device based on magneto‐electric effect and spin Hall effect

Contact Info

Product

Resources

About