Alleviating Thermal Constraints While Maintaining Performance Via Silicon- Based On-chip Optical Interconnects

Abstract

The relentless pursuit of Moore's Law by the semiconductor industry has yielded significant increases in performance, but at the cost of greater power dissipation. As CMOS technology continues to scale, increasing power densities, or "hot spots," particularly in dense logic structures, may limit frequencies below projected targets in order to avoid circuit malfunction. A solution to this problem is to separate the hot spots by interleaving these units with cooler cache banks. This approach, however, increases the distance among processing functions, which can significantly degrade performance. While effort is made to localize communication as much as possible, global communication cannot be completely avoided, particularly in parallel applications.In this paper, the use of silicon-based on-chip optical interconnects is investigated for minimizing the performance gap created by separating processing functions due to thermal constraints. Models of optical components are presented, and used to connect the common front-end with the distributed back-ends of a large-scale Clustered MultiThreaded (CMT) processor. A significant reduction in thermal constraints (translated into an increase in clock frequency), combined with improved instructions per cycle (IPC), is demonstrated over a conventional all-electrical system.