Allocation of multiport memories in data path synthesis

Balakrishnan, M.; Majumdar, A. K.; Banerji, D.; Linders, J. G.; Majithia, J.C.

doi:10.1109/43.3188

Cited by 94 publications

(38 citation statements)

References 6 publications

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“…A handful of systems reported the use of multiport memories for datapath designs. Balakrishnan et al [6] have reported a technique to minimize the number of memory modules. Grouping a maximal number of registers into a cluster, their algorithm assigns a cluster of registers to a multiport memory at a time.…”

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confidence: 99%

A scheduling algorithm for multiport memory minimization in datapath synthesis

Lee¹,

Hwang²

1995

Proceedings of the 1995 Conference on Asia Pacific Design Automation (CD-ROM) - ASP-DAC '95

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-In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps , and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. When compared with previous approaches for several benchmarks available from the literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.hence require less chip area, as compared to random logic. Furthermore, the generated design can be tested easily due to the reduced number of hardware modules. The availability of highdensity and high-speed multiport memories motivates the use of multiport memories in datapath synthesis.Most of the previous approaches allocate variables either to isolated registers or to register files [2][3][4][5]. However, they do not fully utilize the advantages of multiport memories for variable mapping. A handful of systems reported the use of multiport memories for datapath designs. Balakrishnan et al. [6] have reported a technique to minimize the number of memory modules. Grouping a maximal number of registers into a cluster, their algorithm assigns a cluster of registers to a multiport memory at a time. The left-over registers are either allocated to isolated registers or grouped into multiport memories by repeatedly applying the same procedure. The algorithm often leads to nonoptimal register allocations in the number of memory modules and interconnection cost. Wilson et. al. [7] presented a heuristic algorithm in which registers are allocated to available multiport memories one-by-one. Due to the local nature of greedy search, the algorithm does not guarantee an optimal solution in the number of memory modules and the number of registers in each memory module. Ahmad et al.[8] formulated the 0-1 integer linear programming (ILP) to generate the minimum number of multiport memory modules, and tried to reduce the number of registers in each memory module. However, by not considering the connections between multiport memory modules and FUs, the algorithm incurs larger inter-connection cost in the final implementation of datapaths. Kim et al.[9] also used the 0-1 ILP to group variables into multiport memory modules, but they did not try to minimize the number of registers in each memory module. Q. INTRODUCTIONDue to the advance of VLSI circuit fabrication and design techniques, it has been become feasible to realize a large-scale system in a single chip. For the productivity enhancement of design engineers, researchers in the CAD community have been attempting to automa...

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mentioning

confidence: 99%

A scheduling algorithm for multiport memory minimization in datapath synthesis

Lee¹,

Hwang²

1995

Proceedings of the 1995 Conference on Asia Pacific Design Automation (CD-ROM) - ASP-DAC '95

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“…Several memory synthesis tools have also been proposed; however, they are not directly applicable to memory-intensive applications [1,2,7,11,13,16]. For instance, the techniques in [1,2,11] are designed to reduce wiring area by using register les or n-port memories instead of distributed registers; however, only scalar variables are permitted in the input descriptions, and memory hierarchy is not allowed.…”

Section: Previous Workmentioning

confidence: 99%

“…For instance, the techniques in [1,2,11] are designed to reduce wiring area by using register les or n-port memories instead of distributed registers; however, only scalar variables are permitted in the input descriptions, and memory hierarchy is not allowed. In [13], array v ariables are permitted, but the memory model is still not hierarchical.…”

Section: Previous Workmentioning

confidence: 99%

“…(2) Estimate access frequency acc fre q( v) (3) Compute priority(v) = acc fre q( v) =size(v) (4) End for (5) Sort variables on minimum to maximum priority (6) For each variable v in sorted order do (7) Let l be the slowest level of memory (8) Map v to l (9) If execution time constraint is satised do (10) Goto (6) During the level mapping process, all input and output variables are mapped, by default, to the slowest level of memory; however, the user can change this specication if he/she chooses. Note that the variable-to-level mapping completely determines the data-transfer-to-level mapping as well.…”

Section: Variable-to-level Mappingmentioning

confidence: 99%

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Architectural exploration for datapaths with memory hierarchy

Holmes¹,

Gajski²

Proceedings the European Design and Test Conference. ED&TC 1995

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In this paper, we present a new design-space exploration algorithm, the architecture explorer (AE), for analyzing performance/cost t r adeos in memory-intensive applications. AE evaluates FU, bus, and memory cost for a series of performance c onstraints to produce a p erformance/cost tradeo curve. Unlike previous approaches, AE handles both hierarchical and non-hierarchical memory architectures with various speeds of memory.

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“…Most previous work on memory mapping and allocation of multiport memories has been done in the context of data path synthesis and has focused on purely data flow designs (no control constructs) [9,10,11]. These algorithms do not deal with unknown data access patterns because no control flow is involved.…”

Section: Related Workmentioning

confidence: 99%